SNVSCJ3 December   2023 LMR66410 , LMR66420 , LMR66430

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Start-Up, and Shutdown
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Synchronous Buck Regulator at 400 kHz
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1  Choosing the Switching Frequency
        2. 8.2.3.2  Setting the Output Voltage
          1. 8.2.3.2.1 VOUT / FB for Adjustable Output
        3. 8.2.3.3  Inductor Selection
        4. 8.2.3.4  Output Capacitor Selection
        5. 8.2.3.5  Input Capacitor Selection
        6. 8.2.3.6  CBOOT
        7. 8.2.3.7  VCC
        8. 8.2.3.8  CFF Selection
        9. 8.2.3.9  External UVLO
        10. 8.2.3.10 Maximum Ambient Temperature
      4. 8.2.4 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Minimum On-Time (High Input Voltage) Operation

The device continues to regulate output voltage even if the input-to-output voltage ratio requires an on time less than the minimum on time of the chip with a given clock setting. This regulation is accomplished by using valley current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until valley current falls below that determined by the compensation circuit. If the converter is not operating in current limit, the maximum valley current is set above the peak inductor current, preventing valley control from being used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high, such that the inductor current peak value exceeds the peak command dictated by compensation, the high-side device cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit reduces both peak and valley current. After a low enough current is selected by the compensation circuit, valley current matches that being commanded by the compensation circuit. Under these conditions, the low-side device is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley current. Because the on time is fixed at the minimum value, this type of operation resembles that of a device using a constant on-time (COT) control scheme; see Figure 7-20.

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In valley control mode, minimum inductor current is regulated, not peak inductor current.
Figure 7-20 Valley Current Mode Operation