SNOS487F May   2004  – December 2016 LMS8117A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Protection
      2. 7.3.2 Programmable Feedback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Operation With Low Input Voltage
      3. 7.4.3 Operation at Light Loads
      4. 7.4.4 Operation in Self Protection
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Output Regulator
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Capacitors and Stability
            1. Input Bypass Capacitor
            2. ADJUST Pin Bypass Capacitor
            3. Output Capacitor
          2. Output Voltage
          3. Load Regulation
          4. Protection Diodes
        3. Application Curves
      2. 8.2.2 Other Application Circuits
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Heat Sink Requirements
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LMS8117A is a versatile and high-performance linear regulator with a wide temperature range and tight line and load regulation operation. An output capacitor is required to further improve transient response and stability. For the adjustable version, the ADJUST pin can also be bypassed to achieve very high ripple-rejection ratios. The LMS8117A is versatile in its applications, including uses as a post regulator for DC-DC converters, batter chargers, and microprocessor supplies.

Typical Applications

Output Regulator

LMS8117A typ_app_snos487.gif
Required if the regulator is placed far from the power supply filter.
Figure 12. Fixed Output Regulator

Design Requirements

The device component count is very minimal, employing two resistors as part of a voltage divider circuit for the adjustable version and an output capacitor for load regulation. A 10-µF tantalum capacitor on the input is suitable for almost all applications and is required if the regulator is located far from the power-supply filter. An optional bypass capacitor across R2 can also be used to improve PSRR.

Detailed Design Procedure

External Capacitors and Stability

Input Bypass Capacitor

TI recommends an input capacitor. A 10-µF tantalum on the input is a suitable input bypassing for almost all applications.

ADJUST Pin Bypass Capacitor

The ADJUST pin can be bypassed to ground with a bypass capacitor (CADJ) to improve ripple rejection. This bypass capacitor prevents ripple from being amplified as the output voltage is increased. At any ripple frequency, the impedance of the CADJ must be less than R1 to prevent the ripple from being amplified in Equation 1.

Equation 1. 1 / (2 × π × fRIPPLE × CADJ) < R1

The R1 is the resistor between the OUTPUT and the ADJUST pins. Its value is normally from 100 Ω to 200 Ω. For example, with R1 = 124 Ω and fRIPPLE = 120 Hz, the CADJ must be > 11 µF.

Output Capacitor

The output capacitor is critical in maintaining regulator stability, and must meet the required conditions for both minimum amount of capacitance and ESR (Equivalent Series Resistance). The minimum output capacitance required by the LMS8117A is 10 µF, if a tantalum capacitor is used. Any increase of the output capacitance merely improves the loop stability and transient response. The ESR of the output capacitor must be greater than 0.5 Ω and less than 5 Ω. In the case of the adjustable regulator, when the CADJ is used, a larger output capacitance (22-µF tantalum) is required.

Output Voltage

The LMS8117A adjustable version develops a 1.25-V reference voltage (VREF) between the OUTPUT and the ADJUST pins. As shown in Figure 13, this voltage is applied across resistor R1 to generate a constant current I1. The current IADJ from the ADJUST pin could introduce error to the output. Because it is very small (60 µA) compared with the I1 and very constant with line and load changes, the error can be ignored. The constant current I1 then flows through the output set resistor R2 and sets the output voltage to the desired level.

For fixed voltage devices, R1 and R2 are integrated inside the devices.

LMS8117A basic_adjustable_regulator_snos487.gif Figure 13. Basic Adjustable Regulator

VOUT is calculated using Equation 2. IADJ is typically 60 µF and negligible in most applications.

Equation 2. VOUT = VREF × (1 + R2 / R1) + (IADJ × R2)

Load Regulation

The LMS8117A regulates the voltage that appears between its OUTPUT and GROUND pins, or between its OUTPUT and ADJUST pins. In some cases, line resistances can introduce errors to the voltage across the load. To obtain the best load regulation, a few precautions are required.

Figure 14 shows a typical application using a fixed output regulator. The RT1 and RT2 are the line resistances. It is obvious that the VLOAD is less than the VOUT by the sum of the voltage drops along the line resistances (as seen in Equation 3). In this case, the load regulation seen at the RLOAD would be degraded from the data sheet specification. To improve this, the load must be tied directly to the OUTPUT pin on the positive side and directly tied to the GROUND pin on the negative side.

LMS8117A typ_app_fixed_output_reg_snos487.gif Figure 14. Basic Fixed Output Regulator
Equation 3. VLOAD = VOUT – IL × (RT1 + RT2)

When the adjustable regulator is used (Figure 15), the best performance is obtained with the positive side of the resistor R1 tied directly to the OUTPUT pin of the regulator rather than near the load (as seen in Equation 4). This eliminates line drops from appearing effectively in series with the reference and degrading regulation. For example, a 5-V regulator with 0.05-Ω resistance between the regulator and load has a load regulation due to line resistance of 0.05 Ω × IL. If R1 (125 Ω) is connected near the load, the effective line resistance is 0.05 Ω (1 + R2 / R1) or in this case, it is 4 times worse. In addition, the ground side of the resistor R2 can be returned near the ground of the load to provide remote ground sensing and improve load regulation.

LMS8117A best_load_regulation_using_adj_output_reg_snos487.gif Figure 15. Best Load Regulation Using Adjustable Output Regulator
Equation 4. VLOAD = VREF × (R1 + R2) / R1 – (IL × RT1)

Protection Diodes

Under normal operation, the LMS8117A regulators do not require any protection diode. With the adjustable device, the internal resistance between the ADJUST and OUTPUT pins limit the current. No diode is required to divert the current around the regulator even with capacitor on the ADJUST pin. The ADJUST pin can take a transient signal of ±25 V with respect to the output voltage without damaging the device.

When a output capacitor is connected to a regulator and the input is shorted to ground, the output capacitor discharges into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage of the regulator, and rate of decrease of VIN. In the LMS8117A regulators, the internal diode between the OUTPUT and INPUT pins can withstand microsecond surge currents of 10 A to 20 A. With an extremely large output capacitor (≥1000 µF), and with input instantaneously shorted to ground, the regulator could be damaged.

In this case, TI recommends an external diode between the OUTPUT and INPUT pins to protect the regulator, as shown in Figure 16.

LMS8117A reg_protection_diode_snos487.gif Figure 16. Regulator With Protection Diode

Application Curves

LMS8117A graph_12_snos487.gif
SOT-223 package
Figure 17. RθJA vs 1-oz Copper Area
LMS8117A graph_14_snos487.gif
SOT-223 package
Figure 19. Maximum Allowable Power Dissipation
vs Ambient Temperature
LMS8117A graph_16_snos487.gif
SOT-223 package
Figure 21. Maximum Allowable Power Dissipation
vs 1-oz Copper Area
LMS8117A graph_13_snos487.gif
TO-252 package
Figure 18. RθJA vs 2-oz Copper Area
LMS8117A graph_15_snos487.gif
TO-252 package
Figure 20. Maximum Allowable Power Dissipation
vs Ambient Temperature
LMS8117A graph_17_snos487.gif
TO-252 package
Figure 22. Maximum Allowable Power Dissipation
vs 2-oz Copper Area

Other Application Circuits

Figure 23 and Figure 24 show application circuit examples using the LMS8117A devices. Customers must fully validate and test any circuit before implementing a design based on an example in this section. Unless otherwise noted, the design procedures in Output Regulator are applicable.

LMS8117A typ_app_circuits_01_snos487.gif
CADJ is optional, however it will improve ripple rejection.
Figure 23. 1.25-V to 10-V Adjustable Regulator With Improved Ripple Rejection
Equation 5. VOUT = 1.25 × (1 + R2 / R1)
LMS8117A typ_app_circuits_02_snos487.gif
Minimum output is approximately 1.25 V.
Figure 24. 5-V Logic Regulator With Electronic Shutdown