SNOSAQ5H February   2007  – August 2016 LMV551 , LMV552 , LMV554

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: 3 V
    6. 6.6 Electrical Characteristics: 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Voltage and Low Power Operation
      2. 7.3.2 Wide Bandwidth
      3. 7.3.3 Low Input Referred Noise
      4. 7.3.4 Ground Sensing and Rail-to-Rail Output
      5. 7.3.5 Small Size
    4. 7.4 Device Functional Modes
      1. 7.4.1 Stability Of Op Amp Circuits
        1. 7.4.1.1 Stability and Capacitive Loading
          1. 7.4.1.1.1 In the Loop Compensation
          2. 7.4.1.1.2 Compensation by External Resistor
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resource
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN Differential (at V+ = 5 V) ±2.5 V
Supply voltage (V+ – V−) 6 V
Voltage at input/output pins V− –0.3 V+ +0.3 V
Junction temperature, TJ (3) 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications.
(3) The maximum power dissipation is a function of TJ(MAX), θJA, The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±2000 V
Machine model (MM)(2) LMV551 ±100
LMV552 / LMV554 ±250
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.
(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Temperature (1) –40 125 °C
Supply voltage (V+ – V−) 2.7 5.5 V
(1) The maximum power dissipation is a function of TJ(MAX), θJA, The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

6.4 Thermal Information

THERMAL METRIC(1) LMV551 LMV552 LMV554 UNIT
DBV
(SOT-23)		 DCK
(SC70)		 DGK
(VSSOP)		 PW
(TSSOP)
5 PINS 5 PINS 8 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 213.6 303.5 200.3 134.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 174.8 135.5 89.1 60.9 °C/W
RθJB Junction-to-board thermal resistance 72.6 81.1 120.9 77.3 °C/W
ψJT Junction-to-top characterization parameter 56.6 8.4 21.7 11.5 °C/W
ψJB Junction-to-board characterization parameter 72.2 80.4 119.4 76.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: 3 V

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3 V, V− = 0 V, VCM = V+/2 = VO. (1)
PARAMETER TEST CONDITIONS MIN
(2)		 TYP(2) MAX(2) UNIT
VOS Input offset voltage TA = 25°C 1 3 mV
TA = –40°C to 125°C 4.5
TC VOS Input offset average drift TA = –40°C to 125°C 3.3 µV/°C
IB Input bias current(3) TA = 25°C 20 38 nA
IOS Input offset current TA = 25°C 1 20 nA
CMRR Common mode rejection ratio 0 V ≤ VCM 2 V TA = 25°C 74 92 dB
TA = –40°C to +125°C 72
PSRR Power supply rejection ratio 3 ≤ V+ ≤ 5 V,
VCM = 0.5 V		 LMV551 and LMV552 TA = 25°C 80 92 dB
TA = –40°C to +125°C 78
LMV554 TA = 25°C 78 92
TA = –40°C to +125°C 76
2.7 ≤ V+ ≤ 5.5 V,
VCM = 0.5 V		 LMV551 and LMV552 TA = 25°C 80 92
TA = –40°C to +125°C 78
LMV554 TA = 25°C 78 92
TA = -40°C to +125°C 76
CMVR Input common-mode voltage CMRR ≥ 68 dB TA = 25°C 0 2.1 V
CMRR ≥ 60 dB TA = -40°C to +125°C 0 2.1
AVOL Large signal voltage gain 0.4 ≤ VO ≤ 2.6,
RL = 100 kΩ to V+/2		 LMV551 and LMV552 TA = 25°C 81 90 dB
TA = –40°C to +125°C 78
LMV554 TA = 25°C 79 90
TA = –40°C to +125°Ce 77
0.4 ≤ VO ≤ 2.6, RL = 10 kΩ to V+/2 TA = 25°C 71 80
TA = -40°C to +125°C 68
VO Output swing high RL = 100 kΩ to V+/2 TA = 25°C 40 48 mV from rail
TA = –40°C to +125°C 58
RL = 10 kΩ to V+/2 TA = 25°C 85 100
TA = –40°C to +125°C 120
Output swing low RL = 100 kΩ to V+/2 TA = 25°C 50 65
TA = –40°C to +125°C 77
RL = 10 kΩ to V+/2 TA = 25°C 95 110
TA = –40°C to +125°C 130
ISC Output short circuit current Sourcing (5) 10 mA
Sinking (5) 25
IS Supply current per amplifier TA = 25°C 34 42 µA
TA = –40°C to +125°C 52
SR Slew rate AV = +1,
10% to 90% (4)		 1 V/µs
Φm Phase margin RL = 10 kΩ, CL = 20 pF 75 °
GBW Gain bandwidth product 3 MHz
en Input-referred voltage noise f = 100 kHz 70 nV/√Hz
f = 1 kHz 70
In Input-referred current noise f = 100 kHz 0.1 pA/√Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.003%
(1) Electrical Table values apply only for factor testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ = TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) Positive current corresponds to current flowing into the device.
(4) Slew rate is the average of the rising and falling slew rates.
(5) The part is not short-circuit protected and is not recommended for operation with heavy resistive loads.

6.6 Electrical Characteristics: 5 V

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2 = VO. (1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VOS Input offset voltage TA = 25°C 1 3 mV
TA = –40°C to +125°C 4.5
TC VOS Input offset average drift TA = 25°C 3.3 µV/°C
IB Input bias current (4) TA = 25°C 20 38 nA
IOS Input offset current 1 20 nA
CMRR Common mode rejection ratio TA = 25°C 76 93 nA
TA = –40°C to +125°C 74
PSRR Power supply rejection ratio 3 V ≤ V+ ≤ 5 V to VCM = 0.5 V TA = 25°C 78 90 dB
TA = –40°C to +125°C 75
2.7 V ≤ V+ ≤ 5.5 V to VCM = 0.5 V TA = 25°C 78 90
TA = –40°C to +125°C 75
CMVR Input common-mode voltage CMRR ≥ 68 dB
CMRR ≥ 60 dB		 TA = 25°C 0 4.1 V
TA = –40°C to +125°C 0 4.1
AVOL Large signal voltage gain 0.4 ≤ VO ≤ 4.6, RL = 100 kΩ to V+/2 78 90 dB
75
0.4 ≤ VO ≤ 4.6, RL = 10 kΩ to V+/2 75 80
72
VO Output swing high RL = 100 kΩ to V+/2 TA = 25°C 70 92 mV from rail
TA = –40°C to +125°C 122
RL = 10 kΩ to V+/2 TA = 25°C 125 155
TA = –40°C to +125°C 210
Output swing low RL = 100 kΩ to V+/2 TA = 25°C 60 70
TA = –40°C to +125°C 82
RL = 10 kΩ to V+/2 TA = 25°C 110 130
TA = –40°C to +125°C 155
ISC Output short-circuit current Sourcing (5) 10 mA
Sinking (5) 25
IS Supply current per amplifier TA = 25°C 37 46 µA
TA = –40°C to +125°C 54
SR Slew rate AV = +1, VO = 1 VPP
10% to 90% (6)		 1 V/µs
Φm Phase margin RL = 10 kΩ, CL = 20 pF 75 °
GBW Gain bandwidth product 3 MHz
en Input-referred voltage noise f = 100 kHz 70 nV/√Hz
f = 1 kHz 70
In Input-referred current noise f = 100 kHz 0.1 pA/√Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.003%
(1) Electrical Table values apply only for factor testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ = TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) Positive current corresponds to current flowing into the device.
(5) The part is not short-circuit protected and is not recommended for operation with heavy resistive loads.
(6) Slew rate is the average of the rising and falling slew rates.

6.7 Typical Characteristics

LMV551 LMV552 LMV554 20152614.gif
Figure 1. Open-Loop Gain and Phase With Capacitive Load
LMV551 LMV552 LMV554 20152616.gif
Figure 3. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152618.gif
Figure 5. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152620.gif
Figure 7. Small-Signal Transient Response
LMV551 LMV552 LMV554 20152622.gif
Figure 9. Small-Signal Transient Response
LMV551 LMV552 LMV554 20152624.gif
Figure 11. THD+N vs Amplitude at 3 V
LMV551 LMV552 LMV554 20152626.gif
Figure 13. THD+N vs Amplitude
LMV551 LMV552 LMV554 20152628.gif
Figure 15. Supply Current vs Supply Voltage
LMV551 LMV552 LMV554 20152630.gif
Figure 17. VOS vs VCM
LMV551 LMV552 LMV554 20152632.gif
Figure 19. IBIAS vs VCM
LMV551 LMV552 LMV554 20152634.gif
Figure 21. IBIAS vs Supply Voltage
LMV551 LMV552 LMV554 20152636.gif
Figure 23. Negative Output Swing vs Supply Voltage
LMV551 LMV552 LMV554 20152638.gif
Figure 25. Negative Output Swing vs Supply Voltage
LMV551 LMV552 LMV554 20152615.gif
Figure 2. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152617.gif
Figure 4. Open-Loop Gain and Phase With Resistive Load
LMV551 LMV552 LMV554 20152619.gif
Figure 6. Slew Rate vs Supply voltage
LMV551 LMV552 LMV554 20152621.gif
Figure 8. Large-Signal Transient Response
LMV551 LMV552 LMV554 20152623.gif
Figure 10. Input Referred Noise vs Frequency
LMV551 LMV552 LMV554 20152625.gif
Figure 12. THD+N vs Amplitude at 5 V
LMV551 LMV552 LMV554 20152627.gif
Figure 14. THD+N vs Amplitude
LMV551 LMV552 LMV554 20152629.gif
Figure 16. VOS vs VCM
LMV551 LMV552 LMV554 20152631.gif
Figure 18. VOS vs Supply Voltage
LMV551 LMV552 LMV554 20152633.gif
Figure 20. IBIAS vs VCM
LMV551 LMV552 LMV554 20152635.gif
Figure 22. Positive Output Swing vs Supply Voltage
LMV551 LMV552 LMV554 20152637.gif
Figure 24. Positive Output Swing vs Supply Voltage