SNOSAT1I October   2006  – October 2017 LMV841 , LMV842 , LMV844

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - 3.3 V
    6. 6.6 Electrical Characteristics - 5 V
    7. 6.7 Electrical Characteristics - ±5-V
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Protection
      2. 7.3.2 Input Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Driving Capacitive Load
      2. 7.4.2 Noise Performance
    5. 7.5 Interfacing to High Impedance Sensor
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Active Filter Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High-Side, Current-Sensing Circuit
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Thermocouple Sensor Signal Amplification
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)
MIN MAX UNIT
VIN differential –300 300 mV
Supply voltage (V+ – V−) 13.2 V
Voltage at input and output pins V+ + 0.3 V− – 0.3 V
Input current 10 mA
Junction temperature (3) 150 °C
Soldering information  Infrared or convection (20 s) 235 °C
 Wave soldering lead temperature (10 s) 260 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and specifications.
(3) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
Temperature(1) −40 125 °C
Supply voltage (V+ – V−) 2.7 12 V
(1) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

THERMAL METRIC(1) LMV84x UNIT
DCK (SC70) DGK (VSSOP) D (SOIC) PW (TSSOP)
5 PINS 8 PINS 8 PINS 14 PIN 14 PINS
RθJA Junction-to-ambient thermal resistance(2) 269.9 179.2 121.4 85.4 113.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 93.8 69.2 65.7 43.5 38.9 °C/W
RθJB Junction-to-board thermal resistance 48.8 99.7 62.0 39.8 56.3 °C/W
ψJT Junction-to-top characterization parameter 2.0 10.0 16.5 9.2 3.1 °C/W
ψJB Junction-to-board characterization parameter 47.9 98.3 61.4 39.6 55.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6.5 Electrical Characteristics – 3.3 V

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = V+ / 2, and RL > 10 MΩ to V+ / 2.(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VOS Input offset voltage –500 ±50 500 µV
at the temperature extremes –800 800
TCVOS Input offset voltage drift (4) 0.5 µV/°C
at the temperature extremes –5 5
IB Input bias current (4) (5) 0.3 10 pA
at the temperature extremes 300
IOS Input offset current 40 fA
CMRR Common-mode rejection ratio LMV841 0 V ≤ VCM ≤ 3.3 V 84 112 dB
at the temperature extremes 80
Common-mode rejection ratio LMV842 and LMV844 0 V ≤ VCM ≤ 3.3 V 77 106 dB
at the temperature extremes 75
PSRR Power supply rejection ratio 2.7 V ≤ V+ ≤ 12 V, VO = V+ / 2 86 108 dB
at the temperature extremes 82
CMVR Input common-mode voltage range CMRR ≥ 50 dB, at the temperature extremes –0.1 3.4 V
AVOL Large signal voltage gain RL = 2 kΩ
VO = 0.3 V to 3 V		 100 123 dB
at the temperature extremes 96
RL = 10 kΩ
VO = 0.2 V to 3.1 V		 100 131 dB
at the temperature extremes 96
VO Output swing high,
(measured from V+)		 RL = 2 kΩ to V+/2 52 80 mV
at the temperature extremes 120
RL = 10 kΩ to V+/2 28 50 mV
at the temperature extremes 70
Output swing low,
(measured from V−)		 RL = 2 kΩ to V+/2 65 100 mV
at the temperature extremes 120
RL = 10 kΩ to V+/2 33 65 mV
at the temperature extremes 75
IO Output short-circuit current(6)(7) Sourcing VO = V+/2
VIN = 100 mV		 20 32 mA
at the temperature extremes 15
Sinking VO = V+/2
VIN = −100 mV		 20 27 mA
at the temperature extremes 15
IS Supply current Per channel 0.93 1.5 mA
at the temperature extremes 2
SR Slew rate (8) AV = 1, VO = 2.3 VPP
10% to 90%		 2.5 V/µs
GBW Gain bandwidth product 4.5 MHz
Φm Phase margin 67 Deg
en Input-referred voltage noise f = 1 kHz 20 nV/LMV841 LMV842 LMV844 20168399.png
ROUT Open-loop output impedance f = 3 MHz 70 Ω
THD+N Total harmonic distortion + noise f = 1 kHz , AV = 1
RL = 10 kΩ		 0.005%
CIN Input capacitance 7 pF
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
(7) Short circuit test is a momentary test.
(8) Number specified is the slower of positive and negative slew rates.

6.6 Electrical Characteristics – 5 V

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+ / 2, and RL > 10 MΩ to V+ / 2.(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VOS Input offset voltage –500 ±50 500 µV
at the temperature extremes –800 800
TCVOS Input offset voltage drift(4) 0.35 µV/°C
at the temperature extremes –5 5
IB Input bias current(4)(5) 0.3 10 pA
at the temperature extremes 300
IOS Input offset current 40 fA
CMRR Common-mode rejection ratio LMV841 0 V ≤ VCM ≤ 5 V 86 112 dB
at the temperature extremes 80
Common-mode rejection ratio LMV842 and LMV844 0 V ≤ VCM ≤ 5 V 81 106 dB
at the temperature extremes 79
PSRR Power supply rejection ratio 2.7 V ≤ V+ ≤ 12 V, VO = V+/2 86 108 dB
at the temperature extremes 82
CMVR Input common-mode voltage range CMRR ≥ 50 dB, at the temperature extremes –0.2 5.2 V
AVOL Large signal voltage gain RL = 2 kΩ
VO = 0.3V to 4.7 V		 100 125 dB
at the temperature extremes 96
RL = 10 kΩ
VO = 0.2V to 4.8V 		100 133 dB
at the temperature extremes 96
VO Output swing high,
(measured from V+)		 RL = 2 kΩ to V+/2 68 100 mV
at the temperature extremes 120
RL = 10 kΩ to V+/2 32 50 mV
at the temperature extremes 70
Output swing low,
(measured from V–)		 RL = 2 kΩ to V+/2 78 120 mV
at the temperature extremes 140
RL = 10 kΩ to V+/2 38 70 mV
at the temperature extremes 80
IO Output short-circuit current(6) (7) Sourcing VO = V+/2
VIN = 100 mV		 20 33 mA
at the temperature extremes 15
Sinking VO = V+/2
VIN = −100 mV		 20 28 mA
at the temperature extremes 15
IS Supply current Per channel 0.96 1.5 mA
at the temperature extremes 2
SR Slew rate (8) AV = 1, VO = 4 VPP
10% to 90%		 2.5 V/µs
GBW Gain bandwidth product 4.5 MHz
Φm Phase margin 67 Deg
en Input-referred voltage noise f = 1 kHz 20 nV/LMV841 LMV842 LMV844 20168399.png
ROUT Open-loop output impedance f = 3 MHz 70 Ω
THD+N Total harmonic distortion + noise f = 1 kHz , AV = 1
RL = 10 kΩ		 0.003%
CIN Input capacitance 6 pF
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
(7) Short circuit test is a momentary test.
(8) Number specified is the slower of positive and negative slew rates.

6.7 Electrical Characteristics – ±5-V

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = –5 V, VCM = 0 V, and RL > 10 MΩ to VCM.(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VOS Input offset voltage –500 ±50 500 µV
at the temperature extremes –800 800
TCVOS Input offset voltage drift (4) 0.25 µV/°C
at the temperature extremes –5 5
IB Input bias current (4) (5) 0.3 10 pA
at the temperature extremes 300
IOS Input offset current 40 fA
CMRR Common-mode rejection ratio LMV841 –5 V ≤ VCM ≤ 5 V 86 112 dB
at the temperature extremes 80
Common-mode rejection ratio LMV842 and LMV844 –5 V ≤ VCM ≤ 5 V 86 106 dB
at the temperature extremes 80
PSRR Power supply rejection ratio 2.7 V ≤ V+ ≤ 12 V, VO = 0 V 86 108 dB
at the temperature extremes 82
CMVR Input common-mode voltage range CMRR ≥ 50 dB –5.2 5.2 V
AVOL Large signal voltage gain RL = 2 kΩ
VO = −4.7 V to 4.7 V		 100 126 dB
at the temperature extremes 96
RL = 10 kΩ
VO = −4.8 V to 4.8 V		 100 136 dB
at the temperature extremes 96
VO Output swing high,
(measured from V+)		 RL = 2 kΩ to 0 V 95 130 mV
at the temperature extremes 155
RL = 10 kΩ to 0 V 44 75 mV
at the temperature extremes 95
Output swing low,
(measured from V−)		 RL = 2 kΩ to 0 V 105 160 mV
at the temperature extremes 200
RL = 10 kΩ to 0 V 52 80 mV
at the temperature extremes 100
IO Output short-circuit current (6) (7) Sourcing VO = 0 V
VIN = 100 mV		 20 37 mA
at the temperature extremes 15
Sinking VO = 0 V
VIN = −100 mV		 20 29 mA
at the temperature extremes 15
IS Supply current Per channel 1.03 1.7 mA
at the temperature extremes 2
SR Slew rate (8) AV = 1, VO = 9 VPP
10% to 90% 		2.5 V/µs
GBW Gain bandwidth product 4.5 MHz
Φm Phase margin 67 Deg
en Input-referred voltage noise f = 1 kHz 20 nV/LMV841 LMV842 LMV844 20168399.png
ROUT Open-loop output impedance f = 3 MHz 70 Ω
THD+N Total harmonic distortion + noise f = 1 kHz , AV = 1
RL = 10kΩ		 0.006%
CIN Input capacitance 3 pF
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
(7) Short circuit test is a momentary test.
(8) Number specified is the slower of positive and negative slew rates.

6.8 Typical Characteristics

At TA = 25°C, RL = 10 kΩ, VS = 5 V. Unless otherwise specified.
LMV841 LMV842 LMV844 20168310.gif Figure 1. VOS vs VCM Over Temperature at 3.3 V
LMV841 LMV842 LMV844 20168312.gif Figure 3. VOS vs VCM Over Temperature at ±5 V
LMV841 LMV842 LMV844 20168314.gif Figure 5. VOS vs Temperature
LMV841 LMV842 LMV844 20168316.gif Figure 7. Input Bias Current vs VCM
LMV841 LMV842 LMV844 20168318.gif Figure 9. Input Bias Current vs VCM
LMV841 LMV842 LMV844 20168320.gif Figure 11. Sinking Current vs Supply Voltage
LMV841 LMV842 LMV844 20168322.gif Figure 13. Output Swing High vs Supply Voltage RL = 2 kΩ
LMV841 LMV842 LMV844 20168324.gif Figure 15. Output Swing Low vs Supply Voltage RL = 2 kΩ
LMV841 LMV842 LMV844 20168326.gif Figure 17. Output Voltage Swing vs Load Current
LMV841 LMV842 LMV844 20168328.gif Figure 19. Open-Loop Frequency Response Over Load Conditions
LMV841 LMV842 LMV844 20168330.gif Figure 21. PSRR vs Frequency
LMV841 LMV842 LMV844 20168332.gif Figure 23. Channel Separation vs Frequency
LMV841 LMV842 LMV844 20168374.gif Figure 25. Large Signal Step Response With Gain = 10
LMV841 LMV842 LMV844 20168376.gif Figure 27. Small Signal Step Response With Gain = 10
LMV841 LMV842 LMV844 D002_SNOSAT1.gif Figure 29. Overshoot vs CL
LMV841 LMV842 LMV844 20168340.gif Figure 31. THD+N vs Frequency
LMV841 LMV842 LMV844 20168343.gif Figure 33. Closed-Loop Output Impedance vs Frequency
LMV841 LMV842 LMV844 20168311.gif Figure 2. VOS vs VCM Over Temperature at 5 V
LMV841 LMV842 LMV844 20168313.gif Figure 4. VOS vs Supply Voltage
LMV841 LMV842 LMV844 20168315.gif Figure 6. DC Gain vs VOUT
LMV841 LMV842 LMV844 20168317.gif Figure 8. Input Bias Current vs VCM
LMV841 LMV842 LMV844 20168319.gif Figure 10. Supply Current Per Channel vs Supply Voltage
LMV841 LMV842 LMV844 20168321.gif Figure 12. Sourcing Current vs Supply Voltage
LMV841 LMV842 LMV844 20168323.gif Figure 14. Output Swing High vs Supply Voltage RL = 10 kΩ
LMV841 LMV842 LMV844 20168325.gif Figure 16. Output Swing Low vs Supply Voltage RL = 10 kΩ
LMV841 LMV842 LMV844 20168327.gif Figure 18. Open-Loop Frequency Response Over Temperature
LMV841 LMV842 LMV844 D001_SNOSAT1.gif Figure 20. Phase Margin vs CL
LMV841 LMV842 LMV844 20168331.gif Figure 22. CMRR vs Frequency
LMV841 LMV842 LMV844 20168373.gif Figure 24. Large Signal Step Response With Gain = 1
LMV841 LMV842 LMV844 20168375.gif Figure 26. Small Signal Step Response With Gain = 1
LMV841 LMV842 LMV844 20168337.gif Figure 28. Slew Rate vs Supply Voltage
LMV841 LMV842 LMV844 20168339.gif Figure 30. Input Voltage Noise vs Frequency
LMV841 LMV842 LMV844 20168341.gif Figure 32. THD+N vs VOUT