SNAS252S October 2005 – December 2014 LMX2531
The LMX2531 is a low-power, high-performance frequency synthesizer system which includes the PLL, VCO, and partially integrated loop filter. Feature Description gives a discussion of the various blocks of this device.
Because the VCO frequency calibration algorithm is based on clocks from the OSCin pin, there are certain bits that need to be set depending on the OSCin frequency. XTLSEL (R6[22:20]) and XTLDIV (R7[9:8]) are both need to be set based on the OSCin frequency, fOSCin. For some options and for low OSCin frequencies, the XTLMAN (R7[21:10]) and XTLMAN2 (R8) words need to be set to the correct value.
|FREQUENCY||POWERED UP (kΩ)||POWERED DOWN (kΩ)|
The R divider divides the OSCin frequency down to the phase detector frequency. The R divider value, R, is restricted to the values of 1, 2, 4, 8, 16, and 32. If R is greater than 8, then this also puts restrictions on the fractional denominator, FDEN, than can be used. This is discussed in greater depth in later sections.
The phase detector compares the outputs of the R and N dividers and puts out a correction current corresponding to the phase error. The phase detector frequency, fPD, can be calculated as shown in Equation 1.
Choosing R = 1 yields the highest possible phase detector frequency and is optimum for phase noise, although there are restrictions on the maximum phase detector frequency which could force the R value to be larger. The far out PLL noise improves 3 dB for every doubling of the phase detector frequency, but at lower offsets, this effect is much less due to the PLL 1 / f noise. Aside from getting the best PLL phase noise, higher phase detector frequencies also make it easier to filter the noise that the delta-sigma modulator produces, which peaks at an offset frequency of fPD / 2 from the carrier. The LMX2531 also has 16 levels of charge pump currents and a highly flexible fractional modulus. Increasing the charge pump current improves the phase noise about 3 dB per doubling of the charge pump current, although there are small diminishing returns as the charge pump current increases.
From a loop filter design and PLL phase noise perspective, one might think to always design with the highest possible phase detector frequency and charge pump current. However, if one considers the worst case fractional spurs that occur at an output frequency equal to 1 channel spacing away from a multiple of the fOSCin, then this gives reason to reconsider. If the phase detector frequency or charge pump currents are too high, then these spurs could be degraded, and the loop filter may not be able to filter these spurs as well as theoretically predicted. For optimal spur performance, a phase detector frequency around 2.5 MHz and a charge pump current of 1X are recommended.
The N divider in the LMX2531 includes fractional compensation and can achieve any fractional denominator between 1 and 4,194,303. The integer portion, NInteger, is the whole part of the N divider value and the fractional portion, NFractional, is the remaining fraction. So in general, the total N divider value, N, is determined by Equation 2.
For example, if the phase detector frequency (fPD) was 10 MHz and the VCO frequency (fVCO) was 1736.1 MHz, then N would be 173.61. This would imply that NInteger is 173 and NFractional is 61/100. NInteger has some minimum value restrictions that are arise due to the architecture of this divider. The first restrictions arise because the N divider value is actually formed by a quadruple modulus 16/17/20/21 prescaler, which creates minimum divide values. NInteger is further restricted because the LMX2531 due to the fractional engine of the N divider.
The fractional word, NFractional , is a fraction formed with the NUM and DEN words. In the example used here with the fraction of 61/100, NUM = 61 and DEN = 100. The fractional denominator value, DEN, can be set from 2 to 4,194,303. The case of DEN = 0 makes no sense, because this would cause an infinite N value; the case of 1 makes no sense either (but could be done), because integer mode should be used in these applications. All other values in this range, like 10, 32, 42, 734, or 4,000,000 are all valid. Once the fractional denominator, DEN, is determined, the fractional numerator, NUM, is intended to be varied from 0 to DEN-1.
In general, the fractional denominator, DEN, can be calculated by dividing the phase detector frequency by the greatest common divisor (GCD) of the channel spacing (fCH) and the phase detector frequency. If the channel spacing is not obvious, then it can be calculated as the greatest common divisor of all the desired VCO frequencies.
For example, consider the case of a 10 MHz phase detector frequency and a 200 kHz channel spacing at the VCO output. The greatest common divisor of 10 MHz and 200 kHz is just 200 kHz. If one takes 10 MHz divided by 200 kHz, the result is 50. So a fractional denominator of 50, or any multiple of 50 would work in this example. Now consider a case with a 10 MHz phase detector frequency and a 30 kHz channel spacing. The greatest common divisor of 10 MHz and 30 kHz is 10 kHz. The fractional denominator therefore must be a multiple 1000, because this is 10 MHz divided by 10 kHz. For a final example, consider an application with a fixed output frequency of 2110.8 MHz and a OSCin frequency of 19.68 MHz. If the phase detector frequency is chosen to be 19.68 MHz, then the channel spacing can be calculated as the greatest common multiple of 19.68 MHz and 2110.8 MHz, which is 240 kHz. The fractional denominator is therefore a multiple of 41, which is 19.68 MHz / 240 kHz. Refer to AN-1865 Frequency Synthesis and Planning for PLL Architectures (SNAA061) for more details on frequency planning.
To achieve a fractional N value, an integer N divider is modulated between different values. This gives rise to three main degrees of freedom with the LMX2531 delta-sigma engine including the modulator order, dithering, and the way that the fractional portion is expressed. The first degree of freedom is the modulator order, which gives the user the ability to optimize for a particular application. The modulator order can be selected as zero (integer mode), two, three, or four. One simple technique to better understand the impact of the delta-sigma fractional engine on noise and spurs is to tune the VCO to an integer channel and observe the impact of changing the modulator order from integer mode to a higher order. The higher the fractional modulator order is, the lower the spurs theoretically are. However, this is not always the case, and the higher order fractional modulator can sometimes give rise to additional spurious tones, but this is dependent on the application. The second degree of freedom with the LMX2531 delta-sigma engine is dithering. Dithering is often effective in reducing these additional spurious tones, but can add phase noise in some situations. The third degree of freedom is the way that the fraction is expressed. For example, 1/10 can be expressed as 100000/1000000. Expressing the fraction in higher order terms sometimes improves the performance, particularly when dithering is used. In conclusion, there are some guidelines to getting the optimum choice of settings, but these optimum settings are application specific. Refer to AN-1879 Fractional N Frequency Synthesis (SNAA062) for a much more detailed discussion on fractional PLLs and fractional spurs.
The LMX2531 integrates the third pole (formed by R3 and C3) and fourth pole (formed by R4 and C4) of the loop filter. The values for C3, C4, R3, and R4 can also be programmed independently through the MICROWIRE interface and also R3 and R4 can be changed during FastLock, for minimum lock time. The larger the values of these components, the stronger the attenuation of the internal loop filter. The maximum attenuation can be achieved by setting R3 = R4 = 40 kΩ and C3 = C4 = 100 pF while the minimum attenuation is achieved by disabling the loop filter by setting EN_LPFLTR (R6) to zero. Note that when the internal loop filter is disabled, there is still a small amount of input capacitance on front of the VCO on the order of 200 pF.
Because that the internal loop filter is on-chip, it is more effective at reducing certain spurs than the external loop filter. The higher order poles formed by the integrated loop filter are also helpful for attenuating noise due to the delta-sigma modulator. This noise produced by the delta-sigma modulator is outside the loop bandwidth and dependent on the modulator order. Although setting the filtering for maximum attenuation gives the best filtering, it puts increased restrictions on how wide the loop bandwidth of the system can be, which corresponds to the case where the shunt loop filter capacitor, C1, is zero. Increasing the charge pump current and/or the phase detector frequency increases the maximum attainable loop bandwidth when designing with the integrated filter. It is recommended to set the internal loop filter as high as possible without restricting the loop bandwidth of the system more than desired. If some setting between the minimum and maximum value is desired, it is preferable to reduce the resistor values before reducing the capacitor values because this will reduce the thermal noise contribution of the loop filter resistors. For design tools and more information on partially integrated loop filters, go to the Clock Design Tool on www.ti.com.
The LMX2531 includes a fully integrated VCO, including the inductors. For optimum phase noise performance, this VCO has frequency and phase noise calibration algorithms. The frequency calibration algorithm is necessary because the VCO internally divides up the frequency range into several bands, to achieve a lower tuning gain, and therefore better phase noise performance. The frequency calibration routine is activated any time that the R0 register is programmed. There are several bits including LOCKMODE and XTLSEL that need to be set properly for this calibration to be performed in a reliable fashion. If the temperature shifts considerably and the R0 register is not programmed, then it cannot drift more than the maximum allowable drift for continuous lock, ΔTCL, or else the VCO is not ensured to stay in lock. The phase noise calibration algorithm is necessary to achieve the lowest possible phase noise. Each version of the LMX2531, the VCO_ACI_SEL bit (R6[19:16]) needs to be set to the correct value to ensure the best possible phase noise.
The gain of the VCO can change considerably over frequency. It is lowest at the minimum frequency and highest at the maximum frequency. This range is specified in Electrical Characteristics of the data sheet. When designing the loop filter, the following method is recommended to determine what VCO gain to design to. First, take the geometric mean of the minimum and maximum frequencies that are to be used. Then use a linear approximation to extrapolate the VCO gain. Suppose the application requires the LMX2531LQ2080E PLL to tune from 2100 to 2150 MHz. The geometric mean of these frequencies is sqrt (2100 × 2150) MHz = 2125 MHz. The VCO gain is specified as 9 MHz/V at 1904 MHz and 20 MHz/V at 2274 MHz. Over this range of 370 MHz, the VCO gain changes 11 MHz/V. Therefore, at 2125 MHz, the VCO gain would be approximately 9 + (2125 – 1904) × 11 / 370 = 15.6 MHz/V. Although the VCO gain can change from part to part, this variation is small compared to how much the VCO gain can change over frequency.
The VCO frequency is related to the other frequencies and divider values as shown in Equation 4.
All options of the LMX2531 offer the option of dividing the VCO output by two to get half of the VCO frequency at the Fout pin. The channel spacing at the Fout pin is also divided by two as well. Because this divide by two is outside feedback path between the VCO and the PLL, enabling does require one to change the N divider, R divider, or loop filter values. When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise. Note that the R0 register should be reprogrammed the first time after the DIV2 bit is enabled or disabled for optimal phase noise performance. The frequency at the Fout pin is related to the VCO frequency and divider value, D, as shown in Equation 5.
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter. There are several other considerations as well:
The LMX2531 operates mainly in the active mode. The other two modes are reset and powerdown modes. The powerdown mode can be achieved by taking the CE pin to 0 V. The reset mode is achieved if the REG_RST bit is set to 1.
The LMX2531 is programmed using 11 24-bit registers used to control the LMX2531 operation. A 24-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address. The remaining 20 bits form the data field DATA[19:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank. Although there are actually 14 registers in this part, only a portion of them should be programmed, because the state of the other hidden registers (R13, R11, and R10) are set during the initialization sequence. Although it is possible to program these hidden registers, as well as a lot of bits that are defined to either 1 or 0, the user should not experiment with these hidden registers and bits, because the parts are not tested under these conditions and doing so will most likely degrade performance.
The initial loading sequence from a cold start is described in Table 4. The registers must be programmed in order shown. There must be a minimum of 10 ms between the time when R5 is last loaded and R1 is loaded to ensure time for the LDOs to power up properly.
|R12||Program R12 as shown in the complete register map.||1||1||0||0|
|R9||Program R9 as shown in the complete register map.||1||0||0||1|
|R8||See individual section for Register R8 programming information.
Programming of this register is necessary under specific circumstances.
|R7||See individual section for Register R7 programming information.||0||1||1||1|
|R6||See individual section for Register R6 programming information.||0||1||1||0|
|R4||See individual section for Register R4 programming information.
Register R4 only needs to be programmed if FastLock is used.
|R3||See individual section for Register R3 programming information.||0||0||1||1|
|R2||See individual section for Register R2 programming information.||0||0||1||0|
|R1||See individual section for Register R1 programming information.||0||0||0||1|
|R0||See individual section for Register R0 programming information.||0||0||0||0|
The action of programming the R0 register activates a frequency calibration routine for the VCO. This calibration is necessary to get the VCO to center the tuning voltage for optimal performance. If the temperature drifts considerably, then the PLL should stay in lock, provided that the temperature drift specification is not violated.
The NUM word is split between the R0 register and R1 register. The Numerator bits determine the fractional numerator for the delta-sigma PLL. This value can go from 0 to 4095 when the FDM bit (R3) is 0 (the other bits in this register are ignored), or 0 to 4194303 when the FDM bit is 1.
Note that there are restrictions on the fractional numerator value depending on the R divider value if it is 16 or 32.
The N counter is 11 bits. 8 of these bits are located in the R0 register, and the remaining 3 (MSB bits) are located in the R1 register. The LMX2531 consists of an A, B, and C counter, which work in conjunction with the 16/17/20/21 prescaler to form the final N counter value.
|<48||Values less than 48 are prohibited.|
|48 - 51||Possible ONLY with ORDER = 1 (Reset Modulator)|
|52-54||Values of 52 - 54 are prohibited.|
These are the MSB bits in for the fractional numerator that already have been described.
These are the 2 MSB bits for the N counter, which were discussed in Register R0.
This bit programs the charge pump current in from 90 µA to 1440 µA in 90 µA steps. In general, higher charge pump currents yield better phase noise for the PLL, but also can cause higher spurs.
|ICP||CHARGE PUMP STATE|| TYPICAL CHARGE PUMP CURRENT
at 3 VOLTS (µA)
These bits determine the phase detector frequency. The OSCin frequency is divided by this R counter value. Note that only the values of 1, 2, 4, 8, 16, and 32 are allowed.
|n/a||These values are illegal.|
|16||Must be divisible by 2||0||1||0||0||0||0|
|32||Must be divisible by 4||1||0||0||0||0||0|
The R counter value can put some restrictions on the fractional denominator. In the case that it is 16, the fractional denominator must be divisible by 2, which is equivalent to saying that the LSB of the fractional denominator word is zero. In the case that the R counter is 32, the two LSB bits of the fractional denominator word must also be zero, which is equivalent to saying that the fractional denominator must be divisible by 4. Because the fractional denominator can be very large, this should cause no issues. For instance, if one wanted to achieve a fractional word of 1/65, and the R counter value was 16, the fractional word could be changed to 4/260, and the same resolution could be achieved.
These bits determine the fractional denominator. Note that the MSB bits for this word are in register R3. If the FDM bit is set to 0, DEN[21:12] are ignored. The fractional denominator should only be set to zero if the fractional circuitry is being disabled by setting ORDER = 1. A value of one never makes sense to use. All other values could reasonably be used in fractional mode.
These are the MSB bits of the DEN word, which have already been discussed.
The FoLD[3:0] word is used to program the output of the Ftest/LD pin. This pin can be used for a general purpose I/O pin, a lock detect pin, and for diagnostic purposes. When programmed to the digital lock detect state, the output of the Ftest/LD pin will be high when the part is in lock, and low otherwise. Lock is determined by comparing the input phases to the phase detector. The analog lock detect modes put out a high signal with very fast negative pulses, that correspond to when the charge pump comes on. This output can be low pass filtered with an RC filter to determine the lock detect state. If the open drain state is used, a additional pullup resistor is required. For diagnostic purposes, the options that allow one to view the output of the R counter or the N counter can be very useful. Be aware that the output voltage level of the Ftest/LD is not equal to the supply voltage of the part, but rather is given by VOH and VOL in Electrical Characteristics.
|1||Push-Pull||Logical High State|
|2||Push-Pull||Logical Low State|
|3||Push-Pull||Digital Lock Detect|
|5||Push-Pull||N Counter Output Divided by 2|
|6||Open-Drain||Analog Lock Detect|
|7||Push-Pull||Analog Lock Detect|
|14||Push-Pull||R Counter Output|
This bit determines the order of the delta-sigma modulator in the PLL. In general, higher order fractional modulators tend to reduce the primary fractional spurs that occur at increments of the channel spacing, but can also create spurs that are at a fraction of the channel spacing, if there is not sufficient filtering. The optimal choice of modulator order is very application specific, however, a third order modulator is a good starting point if not sure what to try first.
|ORDER||DELTA-SIGMA MODULATOR ORDER|
(Integer Mode - all fractions are ignored)
Dithering is useful in reducing fractional spurs, especially those that occur at a fraction of the channel spacing. The only exception is when the fractional numerator is zero. In this case, dithering usually is not a benefit. Dithering also can sometimes increase the PLL phase noise by a fraction of a dB. In general, if dithering is disabled, phase noise may be slightly better inside the loop bandwidth of the system, but spurs are likely to be worse too.
When this bit is set to 1, the 10 MSB bits for the fractional numerator and denominator are considered. This allows the fractional denominator to range from 1 to 4,194,303. If this bit is set to zero, only the 12 LSB bits of the fractional numerator and denominator are considered, and this allows a fractional denominator from 1 to 4095. When this bit is disabled, the current consumption is about 0.5 mA lower.
When this bit is enabled, the output of the VCO is divided by 2. Enabling this bit does have some impact on harmonic content and output power.
|DIV2||VCO OUTPUT FREQUENCY|
|0||Not Divided by 2|
|1||Divided by 2|
When the value of this word is 3 or less, then FastLock is disabled, and this pin can only be used for general purpose I/O. When this value is 4 or greater, the time-out counter is engaged for the amount of phase detector cycles shown in Table 15.
|TOC VALUE||FLout PIN STATE||TIMEOUT COUNT|
|4||Low||4 × 2 Phase Detector|
|16383||Low||16383 × 2 Phase Detector|
When this count is active, the FLout pin is grounded, the FastLock current is engaged, and the resistors R3 and R4 are also potentially changed. The table below summarizes the bits that control various values in and out of FastLock differences.
|FastLock STATE||FLout||CHARGE PUMP CURRENT||R3||R4|
|Steady State||High Impedance||ICP||R3_ADJ||R4_ADJ|
When FastLock is enabled, this is the charge pump current that is used for faster lock time.
|ICPFL||Fastlock CHARGE PUMP STATE||TYPICAL Fastlock CHARGE PUMP CURRENT at 3 VOLTS (µA)|
When this bit is set to 1 (default), the PLL is powered up, otherwise, it is powered down.
When this bit is set to 1 (default), the VCO is powered up, otherwise, it is powered down.
When this bit is set to 1 (default), the reference oscillator is powered up, otherwise it is powered down.
When this bit is set to 1 (default), the VCO LDO is powered up, otherwise it is powered down.
When this bit is set to 1 (default), the PLL LDO 1 is powered up, otherwise it is powered down.
When this bit is set to 1 (default), the PLL LDO 2 is powered up, otherwise it is powered down.
When this bit is set to 1 (default), the Digital LDO is powered up, otherwise it is powered down.
This bit needs to be programmed three times to initialize the part. When this bit is set to one, all registers are set to default mode, and the part is powered down. The second time the R5 register is programmed with REG_RST = 0, the register reset is released and the default states are still in the registers. However, because the default states for the blocks and LDOs is powered off, it is therefore necessary to program R5 a third time so that all the LDOs and blocks can be programmed to a power up state. When this bit is set to 1, all registers are set to the default modes, but part is powered down. For normal operation, this bit is set to 0. Once this initialization is done, it is not necessary to do this again unless power is removed from the device.
|C3_C4_ADJ||C3 (pF)||C4 (pF)|
|R3_ADJ_FL Value||R3 RESISTOR DURING Fastlock (kΩ)|
|R3_ADJ||R3 VALUE (kΩ)|
|R4_ADJ_FL||R4 VALUE DURING Fast Lock (kΩ)|
|R4_ADJ||R4 VALUE (kΩ)|
The Enable Loop Filter bit is used to enable or disable the third and fourth pole on-chip loop filters.
|EN_LPFLTR||3rd and 4th POLES of LOOP FILTER|
(R3 = R4 = 0 Ω and C3 + C4 = 200 pF)
This bit is used to optimize the VCO phase noise. The recommended values are what are used for all testing purposes, and this bit should be set as instructed in the following table.
|All Other Options||8|
The XTLSEL bit is used to select between manual oscin mode and one of the automatic modes. The user may choose manual oscin mode (XTLSEL = 4) and program the XTLMAN (R7[21:10]) and XTLMAN2 (R7) bits for a specific OSCin frequency, or one of the automatic modes (XTLSEL = 0, 1, 2, 3). For the LMX2531LQ2080E/2570E options or when the OSCin frequency is less than 8 MHz, manual oscin mode must always be selected. The automatic modes can be used for the other frequency options. When using one of the automatic modes, XTLSEL should be set based on the OSCin frequency.
Programming of XTLMAN (R7[21:10]) not required.
Programming of XTLMAN2 (R7) not required.
|8 — 25 MHz|
|1||25 — 50 MHz|
|2||50 — 70 MHz|
|3||70 — 80 MHz|
|4||Manual OSCin Mode
Must use this for LMX2531LQ2080E/2570E/2820E/3010E
Must use this if fOSCin < 8 MHz
Programming of XTLMAN (R7[21:10]) required.
Programming of XTLMAN2 (R7) may be required.
|5 — 80 MHz|
|5, 6, 7||Reserved|
The frequency provided to the VCO frequency calibration circuitry is based on the OSCin frequency divided down by a factor, determined by the XTLDIV word. Note that this division ratio is independent of the R counter value or the phase detector frequency. The necessary division ratio depends on the OSCin frequency and is shown in Table 26.
|XTLDIV||OSCin DIVISION RATIO||OSCin RANGE|
|1||Divide by 2||< 20 MHz|
|2||Divide by 4||20 — 40 MHz|
|3||Divide by 8||> 40 MHz|
XTLMAN must be programmed if word XTLSEL (XTLSEL[2:0] -- OSCin Select) is set to manual OSCin mode. In the table below, the proper value for XTLMAN is shown based on some common OSCin frequencies (fOSCin) and various LMX2531 options. For any OSCin frequency XTLMAN can be calculated as 16 × fOSCin / Kbit. fOSCin is expressed in MHz and Kbit values for the LMX2531 frequency options can be found in Table 28.
|5 MHz||10 MHz||20 MHz||30.72 MHz||61.44 MHz||76.8 MHz|
This bit also adjusts the calibration timing for lock time. In the case that manual mode for XTLSEL is selected and the OSCin frequency is greater than 40 MHz, this bit should be enabled, otherwise it should be 0.
This bit controls the method for which the VCO frequency calibration is done. The two valid modes are linear mode and mixed mode. Linear mode works by searching through the VCO frequency bands in a consecutive manner. Mixed mode works by initially using a divide and conquer approach and then using a linear approach. For small frequency changes, linear mode is faster and for large frequency changes, mixed mode is faster. Linear mode can always be used, but there are restrictions for when Mixed Mode can be used.
|LOCKMODE||DESCRIPTION||CONDITIONS on OPTIONS||CONDITIONS on OSCin FREQUENCY|
|0||Reserved||Never use this mode|
|1||Linear Mode||Works over all options and all valid OSCin Frequencies|
|2||Mixed Mode|| All but the following options
|fOSCin ≥ 8 MHz|
|3||Reserved||Never use this mode|
All the bits in this register should be programmed as shown in Complete Register Content Map.
Even though this register does not have user-selectable bits, it still needs to be programmed. This register should be loaded as shown in Complete Register Content Map.