SNAS680E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.7 Current Consumption Management

The starting point is the typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler bypassed, Pre-R divider bypassed, multiplier bypassed, post-R divider bypassed, 100-MHz phase detector frequency, 0.468-mA charge pump current, channel divider off, one output on, 5400-MHz output frequency, 50-Ω output pullup, 0-dBm output power (differential). To understand current consumption changes due to engaging different functional blocks , refer to Table 8-3.

Table 8-3 Typical Current Consumption Impact By Function
ACTIONSTEPSPROGRAMMINGINCREASE IN CURRENT (mA)
Use input signal pathEnable OSCin doublerOSC_2X = 17
Enable multiplierMULT = 3,4,5, or 610
Add an outputRoute VCO to output BVCO_DISTB_PD = 08
Enable output B bufferOUTB_PD = 054
Increase output power from 0 to +10dBm (differential)Set highest output buffer currentOUTA_POW = 6353
Use channel dividerRoute channel divider to outputCHDIV_DISTA_EN = 15
Enable channel dividerCHDIV_EN = 118
Enable chdiv_seg1CHDIV_SEG1_EN = 12
Enable chdiv_seg2CHDIV_SEG2_EN = 15
Enable chdiv_seg3CHDIV_SEG3_EN = 15