SNAS646G December   2015  – August 2022 LMX2592

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  VCO Doubler
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Distribution
      10. 7.3.10 Output Buffer
      11. 7.3.11 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2592 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.1.1 Understanding Spurs by Offsets

The first step in optimizing spurs is to be able to identify them by offset. Figure 8-1 gives a good example that can be used to isolate the following spur types.

GUID-445551C8-D779-4E27-BF6F-9620F4C31166-low.gifFigure 8-1 Spur Offset Frequency Example

Based on Figure 8-1, the most common spurs can be calculated from the frequencies. Note that the % is the modulus operator and is meant to mean the difference to the closest integer multiple. Some examples of how to use this operator are: 36 % 11 = 3, 1000.1 % 50 = 0.1, and 5023.7 % 122.88 = 14.38. Applying this concept, the spurs at various offsets can be identified from Figure 8-1.

Table 8-1 Spur Definition Table
SPUR TYPEOFFSETOFFSET IN Figure 8-1COMMENTS
OSCinfOSC40 MHzThis spur occurs at harmonics of the OSCin frequency.
FpdfPD120 MHzThe phase detector spur has many possible mechanisms and occurs at multiples of the phase detector frequency.
fOUT % fOSCfOUT % fOSC606.25 % 40 = 6.25 MHzThis spur is caused by mixing between the output and input frequencies.
fVCO% fOSCfVCO % fOSC4850 % 40 = 10 MHzThis spur is caused by mixing between the VCO and input frequencies.
fVCO% fPDfVCO % fPD4850 % 120 = 50 MHzThis spur would be the same offset as the integer boundary spur if PLL_N_PRE=1, but can be different if this value is greater than one.
Integer BoundaryfPD *(Fnum%Fden)/ Fden)120 × (5%24)/24 = 25 MHzThis is a single spur
Primary FractionalfPD / Fden120 / 24 = 5 MHzThe primary fractional
Sub-FractionalfPD / Fden / k

k=2,3, or 6		First Order Modulator: None
2nd Order Modulator: 120/24/2 = 2.5 MHz
3rd Order Modulator: 120/24/6 = 0.83333 MHz
4th Order Modulator: 120/24/12 = 0.416666 MHz		To Calculate k:
1st Order Modulator: k=1
2nd Order Modulator: k=1 if Fden is odd, k=2 if Fden is even
3rd Order Modulator: k=1 if Fden not divisible by 2 or 3, k=2 if Fden divisible by 2 not 3, k=3 if Fden divisible by 3 but not 2, Fden = 6 if Fden divisible by 2 and 3
4th Order Modulator: k=1 if Fden not divisible by 2 or 3. k=3 if Fden divisible by 3 but not 2, k=4 if Fden divisible by 2 but not 3, k=12 if Fden divisible by 2 and 3
Sub-Fractional Spurs exist if k>1

In the case that two different spur types occur at the same offset, either name would be correct. Some may name this by the more dominant cause, while others would simply name by choosing the name that is near the top of Table 8-1.