SNAS646G December   2015  – August 2022 LMX2592

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  VCO Doubler
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Distribution
      10. 7.3.10 Output Buffer
      11. 7.3.11 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2592 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision F (October 2017) to Revision G (August 2022)

  • Changed package description from WQFN to VQFNGo
  • Added a new requirement to Vtune pin descriptionGo
  • Added HD2 and HD3 information to the Electrical Characteristics tableGo
  • Removed sentence: The CLK signal should not be high when LE transitions to lowGo
  • Changed the Channel Divider requirementGo
  • Added a new register field, VTUNE_ADJ, in register R30Go
  • Changed the position of register field, PFD_CTL, in register R13Go
  • Added read only register R68, R69 and R70Go
  • Added additional requirement for register CP_ICOARSE in Table 7-16 Go
  • Added additional information for register MUXOUT_HDRV in Table 7-44 Go
  • Added a new register field, VTUNE_ADJ, in Table 7-25 Go
  • Changed the register R0 FCAL_LPFD_ADJ configurable valuesGo
  • Changed the register R13 PFD_CTL positionGo
  • Added the R68, R69 and R70 register field descriptionsGo
  • Added External Loop Filter sectionGo
  • Moved the Power Supply Recommendations and Layout sections to the Application and Implementation sectionGo

Changes from Revision E (July 2017) to Revision F (October 2017)

  • Switched the RFoutBP and RFoutBM pins in the pinout diagramGo
  • Changed register 7 and the register descriptions of 4, 20 and 46Go

Changes from Revision D (February 2017) to Revision E (July 2017)

  • Changed Channel Divider Setting as a Function of the Desired Output Frequency tableGo

Changes from Revision C (October 2016) to Revision D (January 2017)

  • Removed < 25-µs Fast Calibration Mode bullet from Features Go
  • Changed the high level input voltage minimum value of from: 1.8 to: 1.4 Go
  • Changed text from: the rising edge of the LE signal to: the rising edge of the last CLK signalGo
  • Changed text from: the shift registers to an actual counter to: the shift registers to a register bankGo
  • Added content to the Voltage Controlled Oscillator sectionGo
  • Changed Channel Divider Setting as a Function of the Desired Output Frequency tableGo
  • Changed register 0, 22, and 64 descriptionsGo

Changes from Revision B (July 2016) to Revision C (September 2016)

  • Updated data sheet text to the latest documentation and translations standards Go
  • Changed pin 30 name from: Rext to: NCGo
  • Changed CDM value from: ±1250 V to: ±750 VGo
  • Changed parameter name from: Maximum reference input frequency to: reference input frequencyGo
  • Removed the charge pump current TYP range '0 to 12' and split range into MIN (0) and MAX (12) columnsGo
  • Moved all typical values in the Timing Requirements table to minimum column Go
  • Changed output frequency units from: MHz to: Hz in graphic Go
  • Changed high input value from: 700 to: 200 Go
  • Changed high input value from: 1400 to: 400 Go
  • Changed minimum output frequency step from: Fpd / PLL_DEN to: Fpd × PLL_N_PRE / PLL_DEN / [Channel divider value]Go
  • Changed text from: output dividers to: channel dividers Go
  • Changed output frequency from: 3600 to: 3550 Go
  • Changed VCO frequency from: 7200 to: 7100 Go
  • Changed Phase shift (degrees) from: 360 × MASH_SEED / PLL_N_DEN / [Channel divider value] to: 360 x MASH_SEED x PLL_N_PRE / PLL_N_DEN / [Channel divider value]" Go
  • Changed register 7, 8, 19, 23, 32, 33, 34, 46, and 64 descriptions Go
  • Added registers 20, 22, 25, 59, and 61 Go
  • Changed register descriptions from: Program to default to: Program to Register Map default valuesGo
  • Updated content in the Decreasing Lock Time sectionGo
  • Changed typical application image Go
  • Changed charge pump value from: 4.8 to: 20Go
  • Changed R2 value from: 0.068 to: 68Go

Changes from Revision A (December 2015) to Revision B (July 2016)

  • Added VCO Calibration Time to Electrical Characteristics Go
  • Added registers 2, 4, and 62 to Register Table Go
  • Changed register 38 in Register Table Go
  • Added R2 Register Field Descriptions Go
  • Added R4 Register Field Descriptions Go
  • Added R62 Register Field Descriptions Go

Changes from Revision * (December 2015) to Revision A (December 2015)

  • Changed device status from product preview to production data, and released full data sheet Go