SNAS696C March 2017 – April 2019 LMX2594
The LMX2594 supports the ability to make ramping waveforms using manual mode or automatic mode. In manual mode, the user defines a step and uses the RampClk and RampDir pins to create the ramp. In automatic mode, the user sets up the ramp with up to two linear segments in advance and the device automatically creates this ramp. Table 12 fields apply in both automatic mode and manual pin mode.
|RAMP_EN||0 = Disabled
1 = Enabled
|RAMP_EN must be 1 for any ramping functions to work.|
|RAMP_MANUAL||0 = Automatic ramping mode
1 = Manual pin ramping mode
|In automatic ramping mode, the ramping is automatic and the clock is based on the phase detector. In manual pin ramping mode, the clock is based on rising edges on the RampClk pin.|
|RAMPx_INC||0 to 230 – 1||This is the amount the fractional numerator is increased for each phase detector cycle in the ramp.|
|RAMPx_DLY||0 to 65535||This is the length of the ramp in phase detector cycles.|
|DEALING WITH VCO CALIBRATION|
|RAMP_THRESH||0 to ± 233 – 1||Whenever the fractional numerator changes this much (either positive or negative) because the VCO was last calibrated, the VCO is forced to recalibrate.|
|RAMP_TRIG_CAL||0 = Disabled
1 = Enabled
|When enabled, the VCO is forced to recalibrate at the beginning each ramp.|
|PLL_DEN||4294967295||In ramping mode, the denominator must be fixed to this forced value of 232 – 1. However, the effective denominator in ramping mode is 224.|
|LD_DLY||0||This must be zero to avoid interfering with calibration.|
|0 to ± 233 – 1||2’s complement of the total value of the ramp low and high limits can never go beyond. If this value is exceeded, then the frequency is limited.|
|Phase Detector Frequency|| fOSC/2CAL_CLK_DIV
|Minimum Phase Detector Frequency when Ramping
The phase detector frequency cannot be less than the state machine clock frequency, which is calculated from expression on the left-hand side of the inequality. This is satisfied provided there is no division in the input path. However, if the PLL R-divider is used, it is necessary to adjust CAL_CLK_DIV to adjust the state machine clock frequency. This also implies a maximum R divide of 8 this is the maximum value of 2CAL_CLK_DIV.
Maximum Phase Detector Frequency
TI recommends to set the phase-detector frequency ≤ 125 MHz because, if the phase detector frequency is too high, it can lead to distortion in the ramp. Higher phase-detector frequency may be possible, but this distortion is application specific.