LMX2594

ACTIVE

15 GHz Wideband PLLatinum™ RF Synthesizer with Phase Synchronization and JESD204B support

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Product details

Parameters

Integrated VCO Yes Output frequency (Min) (MHz) 10 Output frequency (Max) (MHz) 15000 Normalized PLL phase noise (dBc/Hz) -236 VCC (V) 3.15 to 3.45 Current consumption (mA) 340 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 open-in-new Find other RF PLLs & synthesizers

Package | Pins | Size

VQFN (RHA) 40 36 mm² 6 x 6 open-in-new Find other RF PLLs & synthesizers

Features

  • 10-MHz to 15-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation

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Description

The LMX2594 is a high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 15 GHz without using an internal doubler, thus eliminating the need for sub-harmonic filters. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2594 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2594 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2594 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

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Same functionality but is not pin-for-pin or parametrically equivalent to the compared device:
LMX2694-EP ACTIVE Enhanced product 15-GHz RF synthesizer with phase synchronization LMX2694-EP has extended temperature operation

Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$399.00
Description

This Evaluation Module is for the LMX2594, which is the first PLL with integrated VCO in industry to get fundamental VCO output up to 15 GHz. The industry leading PLL FOM is -236 dBc/Hz with 1/f of -129 dBc/Hz. This device supports JESD204B standard (it can generate or repeat the SYSREF signal (...)

Features
  • 10 -MHz to 15-GHz Output Frequency 
  • -110 dBc/Hz Phase Noise at 100 kHz Offset with 15 GHz Carrier
  • 45-fs rms Jitter at 7.5GHz (100 Hz to 100 MHz) 
  • Two differential outputs with programmable output power up to 7 dBm at 15 GHz 
  • This EVM has the complete circuit for the synthesizer, optimized and tested for (...)

Software development

APPLICATION SOFTWARE & FRAMEWORKS Download
Texas Instruments PLLatinum Simulator Tool
PLLATINUMSIM-SW The PLLATINUMSIM-SW simulator tool lets you create detailed designs and simulations of our PLLATINUM™ integrated circuits which include the LMX series of PLLs and synthesizers.
Features
  • Part selection based on current, cost, phase noise and package
  • Filter design up for passive and active filters up to 4th-order
  • Simulation of phase noise including PLL, fractional engine, voltage-controlled oscillator (VCO), input, dividers, and loop filter
  • Simulation of spurs including phase detector (...)
APPLICATION SOFTWARE & FRAMEWORKS Download
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Features
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.

Design tools & simulation

SIMULATION MODELS Download
SNAM206.ZIP (44 KB) - IBIS Model
CAD/CAE SYMBOLS Download
SNAR037.ZIP (899 KB)
CAD/CAE SYMBOLS Download
SNAR038.ZIP (3058 KB)
GERBER FILES Download
SNAC084.ZIP (3967 KB)

Reference designs

REFERENCE DESIGNS Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multiple PLL combination reference design for <40-fs jitter (100-Hz to 100-MHz)
TIDA-01346 — The TIDA-01346 design uses two LMX2594 synthesizers in combination to produce lower noise than is possible with just one. By combining the output of two synthesizers that are in phase, a theoretical 3 dB phase noise benefit is possible due to the output power being 6 dB higher while the noise power (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Phase Synchronization Reference Design
TIDA-01410 The TIDA-01410 reference design uses two LMX2594 synthesizers to produce two outputs that are both coherent and adjustable in phase.  Phase coherent outputs are useful for interleaving data converters and also for beam steering applications.  This reference design has identical routing for (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
TIDA-010122 — This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multichannel RF transceiver reference design for radar and electronic warfare applications
TIDA-010132 — This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131 — Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
TIDA-01024 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RHA) 40 View options

Ordering & quality

Support & training

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Videos

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

Posted: 25-Jan-2018
Duration: 09:56

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