Product details

Frequency (max) (MHz) 15000 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Wideband Current consumption (mA) 340 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 15000 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Flexible ramp generation, Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Wideband Current consumption (mA) 340 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFN (RHA) 40 36 mm² 6 x 6
  • 10-MHz to 15-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation
  • 10-MHz to 15-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation

The LMX2594 is a high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 15 GHz without using an internal doubler, thus eliminating the need for sub-harmonic filters. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2594 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2594 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2594 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

The LMX2594 is a high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 15 GHz without using an internal doubler, thus eliminating the need for sub-harmonic filters. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2594 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2594 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2594 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

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Similar functionality to the compared device
LMX1204 ACTIVE 12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization Up to 12.8-GHz clock buffer, multiplier and divider and five-channel JESD support

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet LMX2594 15-GHz Wideband PLLATINUM™ RF Synthesizer With Phase Synchronization and JESD204B Support datasheet (Rev. C) PDF | HTML 17 Apr 2019
Application note VCO Design Basic and Key Parameter for GSM Application PDF | HTML 23 Jan 2026
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 11 Apr 2025
Application brief Compilation of RF Synthesizer Resources PDF | HTML 22 Oct 2024
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Circuit design MASH_SEED Optimization and Impact on Spurs (LMX2820) PDF | HTML 08 Aug 2024
Application brief Using the MSP430FR5969 EVM to Program the LMX2594 PLL Synthesizer PDF | HTML 26 Apr 2024
Application brief LMX2820 with Internal Doubler versus LMX2594 PDF | HTML 16 Jan 2024
Application note Streamline RF Synthesizer VCO Calibration and Optimize PLL Lock Time (Rev. A) 27 Aug 2021
Application note Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization 11 Nov 2020
Application note Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter PDF | HTML 30 Sep 2020
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML 04 Jun 2019
Technical article Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy PDF | HTML 28 Aug 2017
Technical article How to implement FM modulation PDF | HTML 03 Aug 2017
Technical article High-speed data converter clocking for JESD204B PDF | HTML 07 Jul 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

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Evaluation board

LMX2594EVM — LMX2594EVM 15-GHz wideband RF synthesizer with phase synchronization & JESD204B evaluation module

The LMX2594EVM evaluation module (EVM) is a platform for developing the LMX2594. LMX2594 is the first PLL with an integrated voltage-controlled oscillator (VCO) in the industry to get fundamental VCO output up to 15 GHz. The industry leading PLL figure of merit (FOM) is –236 dBc/Hz (...)

User guide: PDF | HTML
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Evaluation board

LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization

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After phase synchronization, the phase of the parts' outputs can be (...)

User guide: PDF | HTML
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Evaluation board

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Support software

TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware

Supported products & hardware

Download options
Simulation model

LMX2594 IBIS Model

SNAM206.ZIP (44 KB) - IBIS Model
CAD/CAE symbol

LMX25xx Reference Pro Altium Database

SNAR037.ZIP (899 KB)
CAD/CAE symbol

LMX2594EVM Altium Database

SNAR038.ZIP (3058 KB)
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design tool

PLLATINUMSIM-SW PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Download options
Gerber file

LMX2594EVM Gerber Files

SNAC084.ZIP (3967 KB)

Many TI reference designs include the LMX2594

Use our reference design selection tool to review and identify designs that best match your application and parameters.

Package Pins CAD symbols, footprints & 3D models
VQFN (RHA) 40 Ultra Librarian

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