SNAS730A March   2018  – November 2018 LMX8410L

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Configurations and Feature Description
        1. 7.3.1.1 RF, LO and IF Interfaces
          1. 7.3.1.1.1 RF Interface
          2. 7.3.1.1.2 LO Interface
            1. 7.3.1.1.2.1 LO Interface as Output Port
            2. 7.3.1.1.2.2 LO Interface as Input Port
          3. 7.3.1.1.3 Baseband Interface
        2. 7.3.1.2 Device Configurations Overview
          1. 7.3.1.2.1 Initialize the Device
          2. 7.3.1.2.2 Configure LO Modes
          3. 7.3.1.2.3 Set Up External LO Clock
          4. 7.3.1.2.4 Perform DCOC (DC Offset Correction)
          5. 7.3.1.2.5 Turn Off SM Clock
          6. 7.3.1.2.6 Perform IMRR (Image Rejection Ratio) Calibration
        3. 7.3.1.3 State Machine Clock
          1. 7.3.1.3.1 Set Divider Values For Internal LO Mode
          2. 7.3.1.3.2 Set Divider Values For External LO Mode
        4. 7.3.1.4 DCOC (DC Offset Correction)
          1. 7.3.1.4.1 RF Input Power Restriction During DCOC
          2. 7.3.1.4.2 Set Up DCOC Clock Divider
        5. 7.3.1.5 Image Rejection Calibration
          1. 7.3.1.5.1 Phase Calibration
          2. 7.3.1.5.2 Gain Calibration
        6. 7.3.1.6 IF Amplifier Common Mode Configurations
        7. 7.3.1.7 Synchronization Mode (Internal LO Mode Only)
          1. 7.3.1.7.1 Synchronization of the LO_OUT Output to the Fosc Input
          2. 7.3.1.7.2 Synchronization of I/Q Outputs to Fosc Inputs Using Internal LO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal LO Mode
        1. 7.4.1.1 VCO Range Uncertainty for 7.5 to 7.7 GHz
      2. 7.4.2 External LO Mode
    5. 7.5 Programming
      1. 7.5.1 General Comments Regarding Programming
      2. 7.5.2 Recommended Initial Power Up Sequence
      3. 7.5.3 Recommended and Power on Reset Bit Values
    6. 7.6 Register Map
      1. 7.6.1  R0 Register (Address = 0x0) [reset = X]
        1. Table 9. R0 Register Field Descriptions
      2. 7.6.2  R1 Register (Address = 0x1) [reset = 0x3]
        1. Table 10. R1 Register Field Descriptions
      3. 7.6.3  R2 Register (Address = 0x2) [reset = X]
        1. Table 11. R2 Register Field Descriptions
      4. 7.6.4  R9 Register (Address = 0x9) [reset = X]
        1. Table 12. R9 Register Field Descriptions
      5. 7.6.5  R10 Register (Address = 0xA) [reset = 0x80]
        1. Table 13. R10 Register Field Descriptions
      6. 7.6.6  R11 Register (Address = 0xB) [reset = 0x10]
        1. Table 14. R11 Register Field Descriptions
      7. 7.6.7  R14 Register (Address = 0xE) [reset = 0x70]
        1. Table 15. R14 Register Field Descriptions
      8. 7.6.8  R36 Register (Address = 0x24) [reset = 0x64]
        1. Table 16. R36 Register Field Descriptions
      9. 7.6.9  R37 Register (Address = 0x25) [reset = 0x200]
        1. Table 17. R37 Register Field Descriptions
      10. 7.6.10 R38 Register (Address = 0x26) [reset = 0x0]
        1. Table 18. R38 Register Field Descriptions
      11. 7.6.11 R39 Register (Address = 0x27) [reset = 0x2710]
        1. Table 19. R39 Register Field Descriptions
      12. 7.6.12 R40 Register (Address = 0x28) [reset = 0x0]
        1. Table 20. R40 Register Field Descriptions
      13. 7.6.13 R41 Register (Address = 0x29) [reset = 0x0]
        1. Table 21. R41 Register Field Descriptions
      14. 7.6.14 R42 Register (Address = 0x2A) [reset = 0x0]
        1. Table 22. R42 Register Field Descriptions
      15. 7.6.15 R43 Register (Address = 0x2B) [reset = 0x0]
        1. Table 23. R43 Register Field Descriptions
      16. 7.6.16 R44 Register (Address = 0x2C) [reset = 0xA2]
        1. Table 24. R44 Register Field Descriptions
      17. 7.6.17 R46 Register (Address = 0x2E) [reset = 0x1]
        1. Table 25. R46 Register Field Descriptions
      18. 7.6.18 R58 Register (Address = 0x3A) [reset = 0x8000]
        1. Table 26. R58 Register Field Descriptions
      19. 7.6.19 R59 Register (Address = 0x3B) [reset = 0x1]
        1. Table 27. R59 Register Field Descriptions
      20. 7.6.20 R69 Register (Address = 0x45) [reset = 0x0]
        1. Table 28. R69 Register Field Descriptions
      21. 7.6.21 R70 Register (Address = 0x46) [reset = 0xC350]
        1. Table 29. R70 Register Field Descriptions
      22. 7.6.22 R75 Register (Address = 0x4B) [reset = 0x0]
        1. Table 30. R75 Register Field Descriptions
      23. 7.6.23 R78 Register (Address = 0x4E) [reset = 0x0]
        1. Table 31. R78 Register Field Descriptions
      24. 7.6.24 R79 Register (Address = 0x4F) [reset = 0x7000]
        1. Table 32. R79 Register Field Descriptions
      25. 7.6.25 R80 Register (Address = 0x50) [reset = 0xA]
        1. Table 33. R80 Register Field Descriptions
      26. 7.6.26 R81 Register (Address = 0x51) [reset = 0x0]
        1. Table 34. R81 Register Field Descriptions
      27. 7.6.27 R82 Register (Address = 0x52) [reset = 0x23]
        1. Table 35. R82 Register Field Descriptions
      28. 7.6.28 R83 Register (Address = 0x53) [reset = 0x2000]
        1. Table 36. R83 Register Field Descriptions
      29. 7.6.29 R84 Register (Address = 0x54) [reset = 0x1900]
        1. Table 37. R84 Register Field Descriptions
      30. 7.6.30 R88 Register (Address = 0x58) [reset = 0x0]
        1. Table 38. R88 Register Field Descriptions
      31. 7.6.31 R94 Register (Address = 0x5E) [reset = 0x8080]
        1. Table 39. R94 Register Field Descriptions
      32. 7.6.32 R95 Register (Address = 0x5F) [reset = X]
        1. Table 40. R95 Register Field Descriptions
      33. 7.6.33 R103 Register (Address = 0x67) [reset = X]
        1. Table 41. R103 Register Field Descriptions
      34. 7.6.34 R110 Register (Address = 0x6E) [reset = X]
        1. Table 42. R110 Register Field Descriptions
      35. 7.6.35 R111 Register (Address = 0x6F) [reset = 0x0]
        1. Table 43. R111 Register Field Descriptions
      36. 7.6.36 R112 Register (Address = 0x70) [reset = 0x0]
        1. Table 44. R112 Register Field Descriptions
      37. 7.6.37 R121 Register (Address = 0x79) [reset = 0x0]
        1. Table 45. R121 Register Field Descriptions
      38. 7.6.38 R123 Register (Address = 0x7B) [reset = 0x3]
        1. Table 46. R123 Register Field Descriptions
      39. 7.6.39 R126 Register (Address = 0x7E) [reset = X]
        1. Table 47. R126 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 High Frequency Trace Routing
      2. 10.1.2 Power Trace Routing
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

High Frequency Trace Routing

  • Design all traces for matched impedance. The single-ended RF trace must be controlled for 50-Ω impedance, while the differential OSCIN, LO, and IF traces must be controlled for 100-Ω differential impedance.
  • Run an uninterrupted ground plane beneath all impedance-controlled traces. No other currents should flow directly under the controlled impedance traces.
  • Keep high-frequency traces as short as possible to minimize losses, or potential for cross-coupling.
  • Controlled impedance can be challenging in materials not designed for RF applications. For example, standard FR-4 has a wide range of acceptable dielectric constants in practice. Although the constants seen in boards from the same panel or material lot code may match very well, this does not ensure that the constants match between different lots or different dielectric manufacturers. Furthermore, FR-4 has a high loss tangent compared to many other materials, which can result in much greater attenuation of high frequency signals across the same distances. TI recommends the use of materials designed specifically for high-frequency use, such as RO4350B or RO4003C from Rogers Corporation.
  • The RF pin is surrounded on three sides by ground pins to assist in the creation of a coplanar waveguide structure. Design the coplanar waveguide to minimize current flow on the ground traces around the pins.
  • The IF outputs are low impedance, and require resistors to set the output impedance.
  • The LO pins are capacitively coupled as inputs, with internal 50-Ω termination. Use 50-Ω pullup resistors to VCC_BUF to bias these pins as inputs, if driven through external capacitors. The LO pins require 50-Ω pullup resistors to VCC_BUF as outputs.
  • The LO pins are located very close to the Q-channel IF pins, and the LO buffer supply is located between these two ports. Placing a bypass capacitor as close as possible to the LO buffer is recommended for proper operation, but this presents a potential problem: vias to VCC and GND must be routed between the differential pairs. Because the high frequency currents in the bypass capacitor and the LO buffer circuit tend to follow the loop with the lowest inductance, and since the VCC via interrupts the path from capacitor ground to IC ground on the plane layer immediately below the top, ground currents tend to travel around this via, in the path of the LO and IF coupling to the plane layer. To maintain the signal integrity of both the LO and IF differential traces, no other currents should be flowing immediately below them on the plane layer. Therefore, the LO bypass capacitor ground via must not connect to the plane layer immediately below the capacitor. TI recommends connecting through the subsequent layer. See the Layout Example section on how this is done.