SNVSC53A December   2021  – June 2025 LP5862

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
      3. 7.3.3 PWM Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

LP5862 LP5862 RSM Package 32-Pin VQFN with Exposed Thermal Pad Top View Figure 5-1 LP5862 RSM Package 32-Pin VQFN with Exposed Thermal Pad Top View
LP5862 LP5862 DBT Package 38-Pin TSSOP Top View Figure 5-2 LP5862 DBT Package 38-Pin TSSOP Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME RSM NO. DBT NO.
VCC 1 14 Power Power supply for device. A 1-μF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
CS0 2 15 O Current sink 0. If not used, this pin must be left floating.
CS1 3 16 O Current sink 1. If not used, this pin must be left floating.
CS2 4 17 O Current sink 2. If not used, this pin must be left floating.
CS3 5 18 O Current sink 3. If not used, this pin must be left floating.
CS4 6 19 O Current sink 4. If not used, this pin must be left floating.
CS5 7 20 O Current sink 5. If not used, this pin must be left floating.
CS6 8 21 O Current sink 6. If not used, this pin must be left floating.
CS7 9 22 O Current sink 7. If not used, this pin must be left floating.
CS8 10 23 O Current sink 8. If not used, this pin must be left floating.
SW0 11/12 25/26 O High-side PMOS switch output 0. Both 2 pins must be tied together. If not used, this pin must be left floating.
SW1 13/14 31/32 O High-side PMOS switch output 1. Both 2 pins must be tied together. If not used, this pin must be left floating.
VLED 15 30 Power Power input for high-side switches.
CS9 16 34 O Current sink 9. If not used, this pin must be left floating.
CS10 17 35 O Current sink 10. If not used, this pin must be left floating.
CS11 18 36 O Current sink 11. If not used, this pin must be left floating.
CS12 19 37 O Current sink 12. If not used, this pin must be left floating.
CS13 20 38 O Current sink 13. If not used, this pin must be left floating.
CS14 21 1 O Current sink 14. If not used, this pin must be left floating.
CS15 22 2 O Current sink 15. If not used, this pin must be left floating.
CS16 23 3 O Current sink 16. If not used, this pin must be left floating.
CS17 24 4 O Current sink 17. If not used, this pin must be left floating.
VCAP 25 6 O Internal LDO output. An 1-μF capacitor must be connected between this pin with GND. Place the capacitor as close to the device as possible.
IFS 26 7 I Interface type select. I2C is selected when IFS is low. SPI is selected when IFS is high. A resistor must be connected between VIO and this pin.
VSYNC 27 8 I External synchronize signal for display mode 2 and mode 3.
SCL_SCLK 28 9 I I2C clock input or SPI clock input. Pull up to VIO when configured as I2C.
SDA_MOSI 29 10 I/O I2C data input or SPI leader output follower input. Pull up to VIO when configured as I2C.
ADDR0_MISO 30 11 I/O I2C address select 0 or SPI leader input follower output.
ADDR1_SS 31 12 I I2C address select 1 or SPI follower select.
VIO_EN 32 13 Power,I Power supply for digital circuits and chip enable. A 1-nF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
GND Exposed Thermal Pad 5/28 Ground Common ground plane.
NC - 24/27/29/33 - No connection.