SLVSGD5 July   2021 LP5890

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Independent and Stackable Mode
        1. 8.3.1.1 Independent Mode
        2. 8.3.1.2 Stackable Mode
      2. 8.3.2 Current Setting
        1. 8.3.2.1 Brightness Control (BC) Function
        2. 8.3.2.2 Color Brightness Control (CC) Function
        3. 8.3.2.3 Choosing BC/CC for a Different Application
      3. 8.3.3 Frequency Multiplier
      4. 8.3.4 Line Transitioning Sequence
      5. 8.3.5 Protections and Diagnostics
        1. 8.3.5.1 Thermal Shutdown Protection
        2. 8.3.5.2 IREF Resistor Short Protection
        3. 8.3.5.3 LED Open Load Detection and Removal
          1. 8.3.5.3.1 LED Open Detection
          2. 8.3.5.3.2 Read LED Open Information
          3. 8.3.5.3.3 LED Open Caterpillar Removal
        4. 8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 8.3.5.4.1 LED Short and Weak Short Detection
          2. 8.3.5.4.2 Read LED Short Information
          3. 8.3.5.4.3 LSD Caterpillar Removal
    4. 8.4 Device Functional Modes
    5. 8.5 Continuous Clock Series Interface
      1. 8.5.1 Data Validity
      2. 8.5.2 CCSI Frame Format
      3. 8.5.3 Write Command
        1. 8.5.3.1 Chip Index Write Command
        2. 8.5.3.2 VSYNC Write Command
        3. 8.5.3.3 Soft_Reset Command
        4. 8.5.3.4 Data Write Command
      4. 8.5.4 Read Command
    6. 8.6 PWM Grayscale Control
      1. 8.6.1 Grayscale Data Storage and Display
        1. 8.6.1.1 Memory Structure Overview
        2. 8.6.1.2 Details of Memory Bank
        3. 8.6.1.3 Write a Frame Data into Memory Bank
      2. 8.6.2 PWM Control for Display
    7. 8.7 Register Maps
      1. 8.7.1  FC0
      2. 8.7.2  FC1
      3. 8.7.3  FC2
      4. 8.7.4  FC3
      5. 8.7.5  FC4
      6. 8.7.6  FC10
      7. 8.7.7  FC11
      8. 8.7.8  FC12
      9. 8.7.9  FC13
      10. 8.7.10 FC14
      11. 8.7.11 FC15
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 System Structure
        2. 9.2.1.2 SCLK Frequency
        3. 9.2.1.3 Internal GCLK Frequency
        4. 9.2.1.4 Line Switch Time
        5. 9.2.1.5 Blank Time Removal
        6. 9.2.1.6 BC and CC
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Chip Index Command
        2. 9.2.2.2 FC Registers Settings
        3. 9.2.2.3 Grayscale Data Write
        4. 9.2.2.4 VSYNC Command
        5. 9.2.2.5 LED Open and Short Read
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7.1 FC0

FC0 is shown in FC0 Register and described in FC0 Register Field Descriptions.

Figure 8-25 FC0 Register
47464544434241403938373635343332
MOD_SIZERESERVEDGRP_DLY_BGRP_DLY_GGRP_DLY_RRESERVED
R/W-00bR-01bR/W-000bR/W-000bR/W-000bR-0bR/W-00b
31302928272625242322212019181716
FREQ_MULFREQ_MODRESERVEDSUBP_NUMSCAN_NUM
R/W-0111bR/W-0bR-000bR/W-000bR/W-01111b
1514131211109876543210
LODRM_ENPSP_MODPS_ENRESERVEDPDC_ENRESERVEDCHIP_NUM
R/W-0bR/W-00bR/W-0bR-000bR/W-1bR-000bR/W-00111b
Table 8-7 FC0 Register Field Descriptions
BitFieldTypeResetDescription
4-0CHIP_NUMR/W00111bSet the device number
00000b: 1 device
...
01111b: 16 devices
...
11111b: 32 devices
7-5RESERVEDR000b
8PDC_ENR/W1bEnable or disable pre-discharge function
0b: disable
1b: enable
11-9RESERVEDR000b
12PS_ENR/W0bEnable or disable the power saving mode
0b: disable
1b: enable
14-13PSP_MODR/W00bSet the powering saving plus mode
00b: disable
01b: save power at high level
10b: save power at middle level
11b: save power at low level
15LODRM_ENR/W0bEnable or disable the LED open load removal function
0b: disable
1b: enable
20-16SCAN_NUMR/W01111bSet the scan line number
00000b: 1 line
...
01111b: 16 lines
...
11111b: 32 lines
23-21SUBP_NUMR/W000bSet the subperiod number
000b: 16
001b: 32
010b: 48
011b: 64
100b: 80
101b: 96
110b: 112
111b: 128
26-24RESERVEDR000b
27FREQ_MODR/W0bSet the GCLK multiplier mode
0b: low frequency mode, 40MHz to 80MHz
1b: high frequency mode, 80MHz to 160MHz
31-28FREQ_MULR/W0111bSet the GCLK multiplier frequency
0000b: 1 x SCLK frequency
...
0111b: 8 x SCLK frequency
...
1111b: 16 x SCLK frequency
34-32RESERVEDR000b
37-35GRP_DLY_RR/W000bSet the Red group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
40-38GRP_DLY_GR/W000bSet the Green group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
43-41GRP_DLY_BR/W000bSet the Blue group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
45-44RESERVEDR01b
47-46MOD_SIZER/W00bSet the module size
00b: 2 devices stackable operation
01b: 1 device non-stackable operation, SCAN_NUM must <=16
10b: 2 devices stackable operation
11b: 3 devices stackable operation