SNVSB23 March   2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 Multi-Phase DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multiphase Operation, Phase Adding, and Phase-Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multiphase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load-Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Sync Clock Functionality
      3. 8.3.3 Power-Up
      4. 8.3.4 Regulator Control
        1. 8.3.4.1 Enabling and Disabling Regulators
        2. 8.3.4.2 Changing Output Voltage
      5. 8.3.5 Enable and Disable Sequences
      6. 8.3.6 Device Reset Scenarios
      7. 8.3.7 Diagnosis and Protection Features
        1. 8.3.7.1 Power-Good Information (PGOOD Pin)
        2. 8.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 8.3.7.2.1 Output Power Limit
          2. 8.3.7.2.2 Thermal Warning
        3. 8.3.7.3 Protection (Regulator Disable)
          1. 8.3.7.3.1 Short-Circuit and Overload Protection
          2. 8.3.7.3.2 Overvoltage Protection
          3. 8.3.7.3.3 Thermal Shutdown
        4. 8.3.7.4 Fault (Power Down)
          1. 8.3.7.4.1 Undervoltage Lockout
      8. 8.3.8 GPIO Signal Operation
      9. 8.3.9 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto-Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  OTP_REV
        2. 8.6.1.2  BUCK0_CTRL1
        3. 8.6.1.3  BUCK1_CTRL1
        4. 8.6.1.4  BUCK2_CTRL1
        5. 8.6.1.5  BUCK3_CTRL1
        6. 8.6.1.6  BUCK0_VOUT
        7. 8.6.1.7  BUCK0_FLOOR_VOUT
        8. 8.6.1.8  BUCK1_VOUT
        9. 8.6.1.9  BUCK1_FLOOR_VOUT
        10. 8.6.1.10 BUCK2_VOUT
        11. 8.6.1.11 BUCK2_FLOOR_VOUT
        12. 8.6.1.12 BUCK3_VOUT
        13. 8.6.1.13 BUCK3_FLOOR_VOUT
        14. 8.6.1.14 BUCK0_DELAY
        15. 8.6.1.15 BUCK1_DELAY
        16. 8.6.1.16 BUCK2_DELAY
        17. 8.6.1.17 BUCK3_DELAY
        18. 8.6.1.18 GPIO2_DELAY
        19. 8.6.1.19 GPIO3_DELAY
        20. 8.6.1.20 RESET
        21. 8.6.1.21 CONFIG
        22. 8.6.1.22 INT_TOP1
        23. 8.6.1.23 INT_TOP2
        24. 8.6.1.24 INT_BUCK_0_1
        25. 8.6.1.25 INT_BUCK_2_3
        26. 8.6.1.26 TOP_STAT
        27. 8.6.1.27 BUCK_0_1_STAT
        28. 8.6.1.28 BUCK_2_3_STAT
        29. 8.6.1.29 TOP_MASK1
        30. 8.6.1.30 TOP_MASK2
        31. 8.6.1.31 BUCK_0_1_MASK
        32. 8.6.1.32 BUCK_2_3_MASK
        33. 8.6.1.33 SEL_I_LOAD
        34. 8.6.1.34 I_LOAD_2
        35. 8.6.1.35 I_LOAD_1
        36. 8.6.1.36 PGOOD_CTRL1
        37. 8.6.1.37 PGOOD_CTRL2
        38. 8.6.1.38 PGOOD_FLT
        39. 8.6.1.39 PLL_CTRL
        40. 8.6.1.40 PIN_FUNCTION
        41. 8.6.1.41 GPIO_CONFIG
        42. 8.6.1.42 GPIO_IN
        43. 8.6.1.43 GPIO_OUT
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Inductor Selection
        2. 9.2.1.2 Input Capacitor Selection
        3. 9.2.1.3 Output Capacitor Selection
        4. 9.2.1.4 Snubber Components
        5. 9.2.1.5 Supply Filtering Components
        6. 9.2.1.6 Current Limit vs. Maximum Output Current
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNF|26
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 Register Descriptions

The LP8752x-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers, their addresses, and their abbreviations are listed in Table 9. A more detailed description is given in the OTP_REV to GPIO_OUT sections.

NOTE

This register map describes the default values for bits that are not read from OTP memory. The orderable code and the default register bit values are defined in part-number specific Technical Reference Manuals.

Table 9. Summary of LP8752x-Q1 Control Registers

Address Register Access D7 D6 D5 D4 D3 D2 D1 D0
0x01 OTP_REV R OTP_ID[7:0]
0x02 BUCK0_CTRL1 R/W EN_BUCK0 EN_PIN_CTRL0 BUCK0_EN_PINSELECT[1:0] EN_ROOF_FLOOR0 EN_RDIS0 BUCK0_FPWM BUCK0_FPWM_MP
0x04 BUCK1_CTRL1 R/W EN_BUCK1 EN_PIN_CTRL1 BUCK1_EN_PINSELECT[1:0] EN_ROOF_FLOOR1 EN_RDIS1 BUCK1_FPWM Reserved
0x06 BUCK2_CTRL1 R/W EN_BUCK2 EN_PIN_CTRL2 BUCK2_EN_PINSELECT[1:0] EN_ROOF_FLOOR2 EN_RDIS2 BUCK2_FPWM BUCK2_FPWM_MP
0x08 BUCK3_CTRL1 R/W EN_BUCK3 EN_PIN_CTRL3 BUCK3_EN_PIN SELECT[1:0] EN_ROOF_FLOOR3 EN_RDIS3 BUCK3_FPWM Reserved
0x0A BUCK0_VOUT R/W BUCK0_VSET[7:0]
0x0B BUCK0_FLOOR_VOUT R/W BUCK0_FLOOR_VSET[7:0]
0x0C BUCK1_VOUT R/W BUCK1_VSET[7:0]
0x0D BUCK1_FLOOR_VOUT R/W BUCK1_FLOOR_VSET[7:0]
0x0E BUCK2_VOUT R/W BUCK2_VSET[7:0]
0x0F BUCK2_FLOOR_VOUT R/W BUCK2_FLOOR_VSET[7:0]
0x10 BUCK3_VOUT R/W BUCK3_VSET[7:0]
0x11 BUCK3_FLOOR_VOUT R/W BUCK3_FLOOR_VSET[7:0]
0x12 BUCK0_DELAY R/W BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0]
0x13 BUCK1_DELAY R/W BUCK1_SHUTDOWN_DELAY[3:0] BUCK1_STARTUP_DELAY[3:0]
0x14 BUCK2_DELAY R/W BUCK2_SHUTDOWN_DELAY[3:0] BUCK2_STARTUP_DELAY[3:0]
0x15 BUCK3_DELAY R/W BUCK3_SHUTDOWN_DELAY[3:0] BUCK3_STARTUP_DELAY[3:0]
0x16 GPIO2_DELAY R/W GPIO2_SHUTDOWN_DELAY[3:0] GPIO2_STARTUP_DELAY[3:0]
0x17 GPIO3_DELAY R/W GPIO3_SHUTDOWN_DELAY[3:0] GPIO3_STARTUP_DELAY[3:0]
0x18 RESET R/W Reserved SW_RESET
0x19 CONFIG R/W DOUBLE_DELAY CLKIN_PD Reserved EN3_PD TDIE_WARN_LEVEL EN2_PD EN1_PD Reserved
0x1A INT_TOP1 R/W Reserved INT_BUCK23 INT_BUCK01 NO_SYNC_CLK TDIE_SD TDIE_WARN INT_OVP I_LOAD_READY
0x1B INT_TOP2 R/W Reserved RESET_REG
0x1C INT_BUCK_0_1 R/W Reserved BUCK1_PG_INT BUCK1_SC_INT BUCK1_ILIM_INT Reserved BUCK0_PG_INT BUCK0_SC_INT BUCK0_ILIM_INT
0x1D INT_BUCK_2_3 R/W Reserved BUCK3_PG_INT BUCK3_SC_INT BUCK3_ILIM_INT Reserved BUCK2_PG_INT BUCK2_SC_INT BUCK2_ILIM_INT
0x1E TOP_STAT R Reserved SYNC_CLK_STAT TDIE_SD_STAT TDIE_WARN_STAT OVP_STAT Reserved
0x1F BUCK_0_1_STAT R BUCK1_STAT BUCK1_PG_STAT Reserved BUCK1_ILIM_STAT BUCK0_STAT BUCK0_PG_STAT Reserved BUCK0_ILIM_STAT
0x20 BUCK_2_3_STAT R BUCK3_STAT BUCK3_PG_STAT Reserved BUCK3_ILIM_STAT BUCK2_STAT BUCK2_PG_STAT Reserved BUCK2_ILIM_STAT
0x21 TOP_MASK1 R/W Reserved Reserved SYNC_CLK_MASK Reserved TDIE_WARN_MASK Reserved I_LOAD_READY_MASK
0x22 TOP_MASK2 R/W Reserved RESET_REG_MASK
0x23 BUCK_0_1_MASK R/W Reserved BUCK1_PG_MASK Reserved BUCK1_ILIM_MASK Reserved BUCK0_PG_MASK Reserved BUCK0_ILIM_MASK
0x24 BUCK_2_3_MASK R/W Reserved BUCK3_PG_MASK Reserved BUCK3_ILIM_MASK Reserved BUCK2_PG_MASK Reserved BUCK2_ILIM_MASK
0x25 SEL_I_LOAD R/W Reserved LOAD_CURRENT_BUCK_SELECT[1:0]
0x26 I_LOAD_2 R Reserved BUCK_LOAD_CURRENT[9:8]
0x27 I_LOAD_1 R BUCK_LOAD_CURRENT[7:0]
0x28 PGOOD_CTRL1 R/W PG3_SEL[1:0] PG2_SEL[1:0] PG1_SEL[1:0] PG0_SEL[1:0]
0x29 PGOOD_CTRL2 R/W HALF_DELAY EN_PG0_NINT PGOOD_SET_DELAY EN_PGFLT_STAT Reserved PGOOD_WINDOW PGOOD_OD PGOOD_POL
0x2A PGOOD_FLT R PG3_FLT PG2_FLT PG1_FLT PG0_FLT
0x2B PLL_CTRL R/W PLL_MODE[1:0] Reserved EXT_CLK_FREQ[4:0]
0x2C PIN_FUNCTION R/W EN_SPREAD_SPEC EN_PIN_CTRL_GPIO3 EN_PIN_SELECT_GPIO3 EN_PIN_CTRL_GPIO2 EN_PIN_SELECT_GPIO2 GPIO3_SEL GPIO2_SEL GPIO1_SEL
0x2D GPIO_CONFIG R/W Reserved GPIO3_OD GPIO2_OD GPIO1_OD Reserved GPIO3_DIR GPIO2_DIR GPIO1_DIR
0x2E GPIO_IN R Reserved GPIO3_IN GPIO2_IN GPIO1_IN
0x2F GPIO_OUT R/W Reserved GPIO3_OUT GPIO2_OUT GPIO1_OUT