SNVS861A February   2014  – August 2014 LP8754

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  General Electrical Characteristics
    6. 6.6  6-Phase Buck Electrical Characteristics
    7. 6.7  6-Phase Buck System Characteristics
    8. 6.8  Protection Features Characteristics
    9. 6.9  I2C Serial Bus Timing Parameters
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Buck Information
    2. 7.2 Functional Block Diagram
    3. 7.3 Features Descriptions
      1. 7.3.1 Multi-Phase DC/DC Converters
        1. 7.3.1.1 Multi-Phase Operation and Phase-Shedding
        2. 7.3.1.2 Transitions Between Low-Power PFM, PFM, and PWM Modes
        3. 7.3.1.3 Buck Converter Load Current
        4. 7.3.1.4 Spread Spectrum Mode
      2. 7.3.2 Power-Up and Output Voltage Sequencing
      3. 7.3.3 Device Reset Scenarios
      4. 7.3.4 Diagnosis and Protection Features
        1. 7.3.4.1 Warnings for Diagnosis (No Power Down)
          1. 7.3.4.1.1 Short-Circuit Protection (SCP)
          2. 7.3.4.1.2 Power Good Monitoring
          3. 7.3.4.1.3 Thermal Warnings
        2. 7.3.4.2 Faults (Fault State and Fast Power Down)
          1. 7.3.4.2.1 Undervoltage Lock-out (UVLO)
          2. 7.3.4.2.2 Overvoltage Protection (OVP)
          3. 7.3.4.2.3 Thermal Shutdown (THSD)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1  Register Descriptions
      2. 7.6.2  VSET_B0
      3. 7.6.3  FPWM
      4. 7.6.4  BUCK0_CTRL
      5. 7.6.5  BUCK1_CTRL
      6. 7.6.6  BUCK2_CTRL
      7. 7.6.7  BUCK3_CTRL
      8. 7.6.8  BUCK4_CTRL
      9. 7.6.9  BUCK5_CTRL
      10. 7.6.10 FLAGS_0
      11. 7.6.11 FLAGS_1
      12. 7.6.12 INT_MASK_0
      13. 7.6.13 GENERAL
      14. 7.6.14 RESET
      15. 7.6.15 DELAY_BUCK0
      16. 7.6.16 CHIP_ID
      17. 7.6.17 PFM_LEV_B0
      18. 7.6.18 PHASE_LEV_B0
      19. 7.6.19 SEL_I_LOAD
      20. 7.6.20 LOAD_CURR
      21. 7.6.21 INT_MASK_2
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 LDO Capacitor Selection
        5. 8.2.2.5 VIOSYS Capacitor Selection
      3. 8.2.3 Application Performance Plots
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

8.1 Application Information

The LP8754 is a multi-phase step-down converter with 6 switcher cores bundled together.

8.2 Typical Application

App_Circuit_LP8754.gifFigure 24. 6-Phase Configuration Schematic

8.2.1 Design Requirements

Table 6 shows requirements for 6-phase configuration.

Table 6. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 2.5 V to 5 V
Output voltage 1.1 V
Converter operation mode Forced PWM
Maximum load current 10 A
Inductor current limit 2.5 A

8.2.2 Detailed Design Procedure

The performance of the LP8754 device depends greatly on the care taken in designing the Printed Circuit Board (PCB). The use of low inductance and low serial resistance ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as possible, because trace inductance, resistance and capacitance can easily become the performance limiting items. The separate power pins VINBXX are not connected together internally. The VINBXX power connections shall be connected together outside the package using power plane construction.

8.2.2.1 Inductor Selection

The DC bias current characteristics of inductors must be considered. Different manufacturers follow different saturation current rating specifications, so attention must be given to details. (Please request DC bias curves from the manufacturer as part of the inductor selection process.) Minimum effective value of inductance to ensure good performance is 0.25 µH at 2.5 A (Default ILIMITP typ.) bias current over the inductor's operating temperature range. The inductor’s DC resistance should be less than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. Table 7 below lists suggested inductors and suppliers. Shielded inductors radiate less noise and are preferable.

Table 7. Suggested Inductors

ITEM MODEL VENDOR DIMENSIONS LxWxH (mm) D.C.R (mΩ) MAX
L0 to L5; Step-down converter inductor 0.47 µH LQM21PNR47MGH
DFE252012 R47
DFE201612C R47N
Murata
TOKO
TOKO
2.0 x 1.2 x 1.0
2.5 x 2 x 1.2
2.0 x 1.6 x 1.2
40 (typ)
39
50

8.2.2.2 Input Capacitor Selection

A ceramic input capacitor of 10 µF, 10 V is sufficient for most applications. Place the input capacitor as close as possible to the VINBXX pin and GND pin of the device. A larger value or higher voltage rating may be used to improve input voltage filtering. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0402. Minimum effective input capacitance to ensure good performance is 2.5 µF at maximum input voltage DC bias including tolerances and over ambient temp range, assuming that there is at least 22 µF of additional capacitance common for all the power input pins on the system power rail.

The input filter capacitor supplies current to the PFET (high-side) switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient ripple current rating.

For additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF between VDDA5V pin and GND is recommended.

Table 8. Suggested Input/Output Capacitors (X5R Dielectric)

MANUFACTURER PART NUMBER VALUE CASE SIZE VOLTAGE RATING
Murata GRM188R60J106ME84 10 µF (20%) 0603 6.3 V
TDK C1608X5R1A106KT 10 µF (10%) 0603 10 V
Taiyo Yuden LMK107BJ106MALTD 10 µF (20%) 0603 10 V
Samsung CL10A226MP8NUNE 22 µF (20%) 0603 10 V
Samsung CL03A105MQ3CSNH 1 µF (20%) 0201 6.3 V

8.2.2.3 Output Capacitor Selection

Use ceramic capacitor, X7R or X5R types; do not use Y5V. DC bias voltage characteristics of ceramic capacitors must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested from them as part of the capacitor selection process. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. Minimum effective output capacitance to ensure good performance in 6-phase configuration is 30 µF at the output voltage DC bias including tolerances and over ambient temp range.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. See suggested capacitors in Table 8.

A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreasing the PFM switching frequency. For most 6-phase applications 4 x 22 µF 0603 capacitors for COUT is suitable. Although the converter's loop compensation can be programmed to adapt to virtually several hundreds of microfarads COUT, an effective COUT less than 120 µF is preferred -- there is not necessarily any benefit to having a COUT higher than 120 µF. Note that the output capacitor may be the limiting factor in the output voltage ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required to settle VOUT down as a consequence of the increased time constant.

8.2.2.4 LDO Capacitor Selection

A ceramic low ESR 1.0-μF capacitor should be connected between the VLDO and GNDA pins

8.2.2.5 VIOSYS Capacitor Selection

Adding a ceramic low ESR 1.0-μF capacitor between the VIOSYS pin and GND is recommended. If VVIOSYS signal is low noisy the capacitor is not required.

8.2.3 Application Performance Plots

Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C

C028_snvs861.png
VIN = 3.7 V Inductor: Murata LQM21PNR47MGH
Figure 25. Efficiency vs Load Current in Forced PWM Mode
C033_snvs861.png
VOUTSET = 900, 1100 and 1300 mV
Inductor: Murata LQM21PNR47MGH
Figure 27. Efficiency vs Load Current in Low-Power PFM Mode, PFM Mode, and Forced PWM Mode
C031_snvs861.png
IOUT = 3 A Inductor: Murata LQM21PNR47MGH
Figure 29. Efficiency vs Input Voltage in PWM Mode
C019_snvs861.png
VOUTSET = 1.1 V
Figure 31. Output Voltage vs Load Current in Forced PWM Mode
C042_snvs861.png
VOUTSET = 1.1 V
Figure 33. Output Voltage vs Temperature
C038_snvs861.png
Figure 35. Phase Currents and Current Balancing Accuracy, 6 Phases Active (Currents measured by LP8754)
C039_snvs861.png
Figure 37. Load Current Measured by LP8754 vs Real Load Current, 6 Phases Active
C014_snvs861.gif
IOUT 1 A → 8 A → 1 A tr = tf = 400 ns
Figure 39. Transient Load Step Response, PWM Mode
C016_snvs861.gif
IOUT 0.5 mA → 0.5 A → 0.5 mA
tr = tf = 100 ns
Figure 41. Transient Load Step Response, AUTO Mode
C008_snvs861.gif
IOUT = 100 µA
Figure 43. Output Voltage Ripple, PFM Mode
C004_snvs861.gif
No Load
Figure 45. Start-up with NRST, Forced PWM
C006_snvs861.gif
No Load
Figure 47. Shutdown with NRST, Forced PWM
C011_snvs861.gif
IOUT 0 A → 5 A → 0 A
Figure 49. Load Ramp
C013_snvs861.gif
Figure 51. Transient from PWM to PFM Mode
C035_snvs861.gif
Figure 53. Metallic Short Applied at VOUT
C029_snvs861.png
VIN = 2.7 V Inductor: Murata LQM21PNR47MGH
Figure 26. Efficiency vs Load Current in Forced PWM Mode
C030_snvs861.png
IOUT = 1 A
Inductor: Murata LQM21PNR47MGH
Figure 28. Efficiency vs Input Voltage in PWM Mode
C032_snvs861.png
IOUT = 6 A Inductor: Murata LQM21PNR47MGH
Figure 30. Efficiency vs Input Voltage in PWM Mode
C026_snvs861.png
VOUTSET = 1.1 V
Figure 32. Output Voltage vs Load Current in PFM/PWM Mode
C037_snvs861.png
ILOAD = 1.0 A VOUTSET = 1.1 V
Figure 34. Line Regulation
C040_snvs861.png
Figure 36. Phase Currents and Current Balancing Accuracy, 3 Phases Active (Currents measured by LP8754)
C041_snvs861.png
Figure 38. Load Current Measured by LP8754 vs Real Load Current, 3 Phases Active
C015_snvs861.gif
IOUT 0.6 A → 2 A → 0.6 A tr = tf = 400 ns
Figure 40. Transient Load Step Response, PWM Mode
C034_SNAS580.gif
VIN 3.3 V → 3.8 V → 3.3 V tr = tf = 10 µs
IOUT = 2000 mA DC
Figure 42. Transient Line Response
C009_snvs861.gif
IOUT = 200 mA
Figure 44. Output Voltage Ripple, PWM Mode, One Phase Active
C005_snvs861.gif
3-A Load
Figure 46. Start-up with NRST, Forced PWM
C007_snvs861.gif
Figure 48. VOUT Transition from 0.6 V to 1.4 V with Different Ramp Settings
C012_snvs861.gif
Figure 50. Transient from PFM to PWM Mode
C036_snvs861.gif
Figure 52. Interrupt Line Going Low with Not Power Good Activation