SNOSD36A August   2017  – December 2017 LPV821

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Low-Side, Always-On Current Sense
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: LPV821 DBV
    2.     Pin Functions: LPV822 DSG (Preview)
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Input
      3. 8.3.3 Internal Offset Correction
      4. 8.3.4 Input Offset Voltage Drift
    4. 8.4 Device Functional Modes
      1. 8.4.1 EMI Performance and Input Filtering
      2. 8.4.2 Driving Capacitive Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Side Current Measurement
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

TA = 25°C, VS = 1.8 V to 3.3 V, VCM = VOUT = VS/2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 3.3 V ±1.5 ±10 μV
dVOS/dT Input offset voltage drift TA = –40°C to 125°C, VS = 3.3 V ±0.02 ±0.096 μV/°C
PSRR Power-supply rejection ratio VS = 1.8 V to 3.3 V 0.4 4.5 μV/V
INPUT
BIAS CURRENT
IB Input bias current +IN TA= 25°C 7 pA
TA= 125°C 7
-IN TA= 25°C -7
TA= 125°C -250
IOS Input offset current 14 pA
NOISE
En Input voltage noise f = 0.1 Hz to 10 Hz 3.9 μVPP
en Input voltage noise density f = 100 Hz 215 nV/√Hz
in Input current noise density f = 100 Hz 1 fA/√Hz
INPUT
VOLTAGE
VCM Common-mode voltage range (V–) (V+) V
CMRR Common-mode rejection ratio (V–) ≤ VCM ≤ (V+), VS = 3.3 V 100 125 dB
INPUT
CAPACITANCE
Differential 3.3 pF
Common-mode 3.7 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.1 V ≤ VO ≤ (V+) – 0.1 V, RL = 100 kΩ to VS / 2 135 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product CL = 20 pF, RL = 10 MΩ 8 kHz
SR Slew rate G = +1, CL = 20 pF 3.3 V/ms
OUTPUT
VOH Voltage output swing from positive rail RL = 100 kΩ to V+/2, VS = 3.3 V 12 mV
VOL Voltage output swing from negative rail RL = 100 kΩ to V+/2, VS = 3.3 V 12
ISC Short-circuit current Sourcing, VO to V–, VIN (diff) = 100 mV, VS = 3.3 V 21 mA
Sinking, VO to V+, VIN (diff) = –100 mV, VS = 3.3 V 50
CL Capacitive load drive See Table 1
ZO Open-loop output impedance ƒ = 100 Hz, IO = 0 A 80 kΩ
POWER
SUPPLY
IQ Quiescent current per channel VCM = VS/2, IO = 0, VS = 3.3 V 650 790 nA