SLLSFV2 August   2023 MCF8316C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Reference Profiles
          2. 7.3.8.5.2 Staircase Speed Profile
          3. 7.3.8.5.3 Forward-Reverse Speed Profile
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Torque Mode
        5. 7.3.11.5 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Active Braking
      16. 7.3.16 Output PWM Switching Frequency
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Low-Side Braking
        3. 7.3.19.3 High-Side Braking
        4. 7.3.19.4 Active Spin-Down
        5. 7.3.19.5 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG during Open and Closed Loop States
        3. 7.3.20.3 FG during Fault and Idle States
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.22.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.22.10 FET Thermal Warning (OTW)
        11. 7.3.22.11 FET Thermal Shutdown (TSD_FET)
        12. 7.3.22.12 Motor Lock (MTR_LCK)
          1. 7.3.22.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.22.13 Motor Lock Detection
          1. 7.3.22.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.13.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.22.14 MPET Faults
        15. 7.3.22.15 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Anti voltage surge (AVS)
        6. 8.2.1.6 Real time variable tracking using DACOUT
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.2 Fault_Configuration Registers

Table 7-30 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in Table 7-30 should be considered as reserved locations and the register contents should not be modified.

Table 7-30 FAULT_CONFIGURATION Registers
Offset Acronym Register Name Section
90h FAULT_CONFIG1 Fault Configuration1 Go
92h FAULT_CONFIG2 Fault Configuration2 Go

Complex bit access types are encoded to fit into small table cells. Table 7-31 shows the codes that are used for access types in this section.

Table 7-31 Fault_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.2.1 FAULT_CONFIG1 Register (Offset = 90h) [Reset = 00000000h]

FAULT_CONFIG1 is shown in Figure 7-70 and described in Table 7-32.

Return to the Summary Table.

Register to configure fault settings1

Figure 7-70 FAULT_CONFIG1 Register
3130292827262524
RESERVEDILIMITHW_LOCK_ILIMIT
R/W-0hR/W-0hR/W-0h
2322212019181716
HW_LOCK_ILIMITLOCK_ILIMITLOCK_ILIMIT_MODE
R/W-0hR/W-0hR/W-0h
15141312111098
LOCK_ILIMIT_MODELOCK_ILIMIT_DEGLCK_RETRY
R/W-0hR/W-0hR/W-0h
76543210
LCK_RETRYMTR_LCK_MODEIPD_TIMEOUT_FAULT_ENIPD_FREQ_FAULT_ENSATURATION_FLAGS_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-32 FAULT_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30-27ILIMITR/W0h Current limit for Iq axis (torque) current reference in closed loop
0h = 0.125 A
1h = 0.25 A
2h = 0.5 A
3h = 1.0 A
4h = 1.5 A
5h = 2.0 A
6h = 2.5 A
7h = 3.0 A
8h = 3.5 A
9h = 4.0 A
Ah = 4.5 A
Bh = 5.0 A
Ch = 5.5 A
Dh = 6.0 A
Eh = 7.0 A
Fh = 8.0 A
26-23HW_LOCK_ILIMITR/W0h Comparator based lock detection current threshold
0h = 0.125 A
1h = 0.25 A
2h = 0.5 A
3h = 1.0 A
4h = 1.5 A
5h = 2.0 A
6h = 2.5 A
7h = 3.0 A
8h = 3.5 A
9h = 4.0 A
Ah = 4.5 A
Bh = 5.0 A
Ch = 5.5 A
Dh = 6.0 A
Eh = 7.0 A
Fh = 8.0 A
22-19LOCK_ILIMITR/W0h ADC based lock detection current threshold
0h = 0.125 A
1h = 0.25 A
2h = 0.5 A
3h = 1.0 A
4h = 1.5 A
5h = 2.0 A
6h = 2.5 A
7h = 3.0 A
8h = 3.5 A
9h = 4.0 A
Ah = 4.5 A
Bh = 5.0 A
Ch = 5.5 A
Dh = 6.0 A
Eh = 7.0 A
Fh = 8.0 A
18-15LOCK_ILIMIT_MODER/W0h Lock current limit mode
0h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated
1h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated
2h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in high side brake mode (All high side FETs are turned ON)
3h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON)
4h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
6h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in high side brake mode (All high side FETs are turned ON); nFAULT active
7h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active
8h = Ilimit lock detection current limit is in report only but no action is taken; nFAULT active
9h = ILIMIT LOCK is disabled
Ah = ILIMIT LOCK is disabled
Bh = ILIMIT LOCK is disabled
Ch = ILIMIT LOCK is disabled
Dh = ILIMIT LOCK is disabled
Eh = ILIMIT LOCK is disabled
Fh = ILIMIT LOCK is disabled
14-11LOCK_ILIMIT_DEGR/W0h Lock detection current limit deglitch time
0h = Not Applicable
1h = Not Applicable
2h = 0.2 ms
3h = 0.5 ms
4h = 1 ms
5h = 2.5 ms
6h = 5 ms
7h = 7.5 ms
8h = 10 ms
9h = 25 ms
Ah = 50 ms
Bh = 75 ms
Ch = 100 ms
Dh = 200 ms
Eh = 500 ms
Fh = 1000 ms
10-7LCK_RETRYR/W0h Lock detection retry time
0h = 300 ms
1h = 500 ms
2h = 1 s
3h = 2 s
4h = 3 s
5h = 4 s
6h = 5 s
7h = 6 s
8h = 7 s
9h = 8 s
Ah = 9 s
Bh = 10 s
Ch = 11 s
Dh = 12 s
Eh = 13 s
Fh = 14 s
6-3MTR_LCK_MODER/W0h Motor Lock Mode
0h = Motor lock detection causes latched fault; nFAULT active; Gate driver is tristated
1h = Motor lock detection causes latched fault; nFAULT active; Gate driver is tristated
2h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in high side brake mode (All high side FETs are turned ON)
3h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON)
4h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
6h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in high side brake mode (All high side FETs are turned ON); nFAULT active
7h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active
8h = Motor lock detection current limit is in report only but no action is taken; nFAULT active
9h = Motor lock detection is disabled
Ah = Motor lock detection is disabled
Bh = Motor lock detection is disabled
Ch = Motor lock detection is disabled
Dh = Motor lock detection is disabled
Eh = Motor lock detection is disabled
Fh = Motor lock detection is disabled
2IPD_TIMEOUT_FAULT_ENR/W0h IPD timeout fault enable
0h = Disable
1h = Enable
1IPD_FREQ_FAULT_ENR/W0h IPD frequency fault enable
0h = Disable
1h = Enable
0SATURATION_FLAGS_ENR/W0h Enables indication of current loop and speed loop saturation
0h = Disable
1h = Enable

7.7.2.2 FAULT_CONFIG2 Register (Offset = 92h) [Reset = 00000000h]

FAULT_CONFIG2 is shown in Figure 7-71 and described in Table 7-33.

Return to the Summary Table.

Register to configure fault settings2

Figure 7-71 FAULT_CONFIG2 Register
3130292827262524
RESERVEDLOCK1_ENLOCK2_ENLOCK3_ENLOCK_ABN_SPEEDABNORMAL_BEMF_THR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ABNORMAL_BEMF_THRNO_MTR_THRHW_LOCK_ILIMIT_MODE
R/W-0hR/W-0hR/W-0h
15141312111098
HW_LOCK_ILIMIT_MODEHW_LOCK_ILIMIT_DEGRESERVEDMIN_VM_MOTOR
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
MIN_VM_MODEMAX_VM_MOTORMAX_VM_MODEAUTO_RETRY_TIMES
R/W-0hR/W-0hR/W-0hR/W-0h
Table 7-33 FAULT_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h Reserved
30LOCK1_ENR/W0h Lock 1 (Abnormal Speed) Enable
0h = Disable
1h = Enable
29LOCK2_ENR/W0h Lock 2 (Abnormal BEMF) Enable
0h = Disable
1h = Enable
28LOCK3_ENR/W0h Lock 3 (No Motor) Enable
0h = Disable
1h = Enable
27-25LOCK_ABN_SPEEDR/W0h Abnormal speed lock threshold (% of MAX_SPEED)
0h = 130%
1h = 140%
2h = 150%
3h = 160%
4h = 170%
5h = 180%
6h = 190%
7h = 200%
24-22ABNORMAL_BEMF_THRR/W0h Abnormal BEMF lock threshold (% of expected BEMF)
0h = 40%
1h = 45%
2h = 50%
3h = 55%
4h = 60%
5h = 65%
6h = 67.5%
7h = 70%
21-19NO_MTR_THRR/W0h No motor lock threshold
0h = 0.075 A
1h = 0.075 A
2h = 0.1A
3h = 0.125 A
4h = 0.25 A
5h = 0.5 A
6h = 0.75 A
7h = 1.0 A
18-15HW_LOCK_ILIMIT_MODER/W0h Hardware lock detection current mode
0h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated
1h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated
2h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in high side brake mode (All high side FETs are turned ON)
3h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON)
4h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
6h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in high side brake mode (All high side FETs are turned ON); nFAULT active
7h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active
8h = Hardware ILIMIT lock detection is in report only but no action is taken
9h = Hardware ILIMIT lock detection is disabled
Ah = Hardware ILIMIT lock detection is disabled
Bh = Hardware ILIMIT lock detection is disabled
Ch = Hardware ILIMIT lock detection is disabled
Dh = Hardware ILIMIT lock detection is disabled
Eh = Hardware ILIMIT lock detection is disabled
Fh = Hardware ILIMIT lock detection is disabled
14-12HW_LOCK_ILIMIT_DEGR/W0h Hardware lock detection current limit deglitch time
0h = No deglitch
1h = 1 µs
2h = 2 µs
3h = 3 µs
4h = 4 µs
5h = 5 µs
6h = 6 µs
7h = 7 µs
11RESERVEDR/W0h Reserved
10-8MIN_VM_MOTORR/W0h Minimum DC Bus voltage for running motor (V)
0h = No Limit
1h = 4.5 V
2h = 5 V
3h = 5.5 V
4h = 6 V
5h = 7.5 V
6h = 10 V
7h = 12.5 V
7MIN_VM_MODER/W0h DC Bus Undervoltage Fault Recovery Mode
0h = Latch on undervoltage
1h = Automatic clear if voltage in bounds
6-4MAX_VM_MOTORR/W0h Maximum DC Bus voltage for running motor
0h = No Limit
1h = 20 V
2h = 22.5 V
3h = 25 V
4h = 27.5 V
5h = 30 V
6h = 32.5 V
7h = 35 V
3MAX_VM_MODER/W0h DC Bus Overvoltage Fault Recovery Mode
0h = Latch on overvoltage
1h = Automatic clear if voltage in bounds
2-0AUTO_RETRY_TIMESR/W0h Automatic retry attempts
0h = No Limit
1h = 2
2h = 3
3h = 5
4h = 7
5h = 10
6h = 15
7h = 20