SLLSFP7A december   2022  – april 2023 MCT8315A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Under Voltage Protection
        7. 7.3.3.7 Buck Over Current Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Speed Control
        1. 7.3.8.1 Analog Mode Speed Control
        2. 7.3.8.2 PWM Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency Mode Speed Control
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 120o Commutation
          1. 7.3.11.1.1 High-Side Modulation
          2. 7.3.11.1.2 Low-Side Modulation
          3. 7.3.11.1.3 Mixed Modulation
        2. 7.3.11.2 Variable Commutation
        3. 7.3.11.3 Lead Angle Control
        4. 7.3.11.4 Closed loop accelerate
      12. 7.3.12 Speed Loop
      13. 7.3.13 Input Power Regulation
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Fast Start-up (< 50 ms)
        1. 7.3.16.1 BEMF Threshold
        2. 7.3.16.2 Dynamic Degauss
      17. 7.3.17 Fast Deceleration
      18. 7.3.18 Active Demagnetization
        1. 7.3.18.1 Active Demagnetization in action
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 Protections
        1. 7.3.21.1  VM Supply Undervoltage Lockout
        2. 7.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.21.5  Overvoltage Protection (OVP)
        6. 7.3.21.6  Overcurrent Protection (OCP)
          1. 7.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.21.7  Buck Overcurrent Protection
        8. 7.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.21.10 Thermal Warning (OTW)
        11. 7.3.21.11 Thermal Shutdown (TSD)
        12. 7.3.21.12 Motor Lock (MTR_LCK)
          1. 7.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.21.13 Motor Lock Detection
          1. 7.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.21.14 SW VM Undervoltage Protection
        15. 7.3.21.15 SW VM Overvoltage Protection
        16. 7.3.21.16 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 120o and variable commutation
        3. 8.2.1.3 Faster startup time
        4. 8.2.1.4 Setting the BEMF threshold
        5. 8.2.1.5 Maximum speed
        6. 8.2.1.6 Faster deceleration
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.4 Gate_Driver_Configuration Registers

Table 7-34 lists the memory-mapped registers for the Gate_Driver_Configuration registers. All register offset addresses not listed in Table 7-34 should be considered as reserved locations and the register contents should not be modified.

Table 7-34 GATE_DRIVER_CONFIGURATION Registers
OffsetAcronymRegister NameSection
AChGD_CONFIG1Gate driver configuration 1GD_CONFIG1 Register (Offset = ACh) [Reset = 00228000h]
AEhGD_CONFIG2Gate driver configuration 2GD_CONFIG2 Register (Offset = AEh) [Reset = 01200000h]

Complex bit access types are encoded to fit into small table cells. Table 7-35 shows the codes that are used for access types in this section.

Table 7-35 Gate_Driver_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.4.1 GD_CONFIG1 Register (Offset = ACh) [Reset = 00228000h]

GD_CONFIG1 is shown in Figure 7-74 and described in Table 7-36.

Return to the Summary Table.

Register to configure gated driver settings1

Figure 7-74 GD_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDSLEW_RATERESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CLR_FLTRESERVEDRESERVEDRESERVEDOVP_SELOVP_ENRESERVEDOTW_REP
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
15141312111098
RESERVEDRESERVEDOCP_DEGOCP_RETRYOCP_LVLOCP_MODE
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
BEMF_THRRESERVEDADCOMP_TH_LSADCOMP_TH_HSEN_ASREN_AARCSA_GAIN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-36 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29RESERVEDR/W0h Reserved
28RESERVEDR/W0h Reserved
27-26SLEW_RATER/W0h Slew rate
0h = 25 V/µs
1h = 50 V/µs
2h = 125 V/µs
3h = 200 V/µs
25-24RESERVEDR/W0h Reserved
23CLR_FLTR/W0h Clear fault
0h = No clear fault command is issued
1h = To clear the latched fault bits. This bit automatically resets after being written.
22RESERVEDR/W0h Reserved
21RESERVEDR/W1h Reserved
20RESERVEDR/W0h Reserved
19OVP_SELR/W0h Overvoltage protection level
0h = VM overvoltage level is 34-V
1h = VM overvoltage level is 22-V
18OVP_ENR/W0h Overvoltage protection enable
0h = Disable
1h = Enable
17RESERVEDR/W1h Reserved
16OTW_REPR/W0hOvertemperature warning reporting on nFAULT
0h = Over temperature reporting on nFAULT is disabled
1h = Over temperature reporting on nFAULT is enabled
15RESERVEDR/W1h Reserved
14RESERVEDR/W0h Reserved
13-12OCP_DEGR/W0h OCP deglitch time
0h = 0.2 µs
1h = 0.6 µs
2h = 1.2 µs
3h = 1.6 µs
11OCP_RETRYR/W0h OCP retry time
0h = 5 ms
1h = 500 ms
10OCP_LVLR/W0h OCP level
0h = 9 A (Typical)
1h = 13 A (Typical)
9-8OCP_MODER/W0h OCP fault mode
0h = Overcurrent causes a latched fault
1h = Overcurrent causes an automatic retrying fault
2h = Overcurrent is report only but no action is taken
3h = Overcurrent is not reported and no action is taken
7BEMF_THRR/W0h BEMF comparator threshold
0h = BEMF comparator threshold is 20 mV
1h = BEMF comparator threshold is 100 mV
6RESERVEDR/W0h Reserved
5ADCOMP_TH_LSR/W0h Active demag comparator threshold for low-side
0h = 100 mA
1h = 150 mA
4ADCOMP_TH_HSR/W0h Active demag comparator threshold for high-side
0h = 100 mA
1h = 150 mA
3EN_ASRR/W0h Active synchronous rectification enable
0h = Disable
1h = Enable
2EN_AARR/W0h Active asynchronous rectification enable
0h = Disable
1h = Enable
1-0CSA_GAINR/W0h Current Sense Amplifier (CSA) Gain
0h = 0.24 V/A
1h = 0.48 V/A
2h = 0.96 V/A
3h = 1.92 V/A

7.7.4.2 GD_CONFIG2 Register (Offset = AEh) [Reset = 01200000h]

GD_CONFIG2 is shown in Figure 7-75 and described in Table 7-37.

Return to the Summary Table.

Register to configure gated driver settings2

Figure 7-75 GD_CONFIG2 Register
3130292827262524
PARITYDELAY_COMP_ENTARGET_DELAYRESERVEDBUCK_PS_DIS
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
2322212019181716
BUCK_CLBUCK_SELRESERVEDRESERVED
R/W-0hR/W-1hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVED
R/W-0h
Table 7-37 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30DELAY_COMP_ENR/W0h Driver delay compensation enable
0h = Disable
1h = Enable
29-26TARGET_DELAYR/W0h Target delay
0h = Automatic based on slew rate
1h = 0.4 µs
2h = 0.6 µs
3h = 0.8 µs
4h = 1 µs
5h = 1.2 µs
6h = 1.4 µs
7h = 1.6 µs
8h = 1.8 µs
9h = 2 µs
Ah = 2.2 µs
Bh = 2.4 µs
Ch = 2.6 µs
Dh = 2.8 µs
Eh = 3 µs
Fh = 3.2 µs
25RESERVEDR/W0h Reserved
24BUCK_PS_DISR/W1h Buck power sequencing disable
0h = Buck power sequencing is enabled
1h = Buck power sequencing is disabled
23BUCK_CLR/W0h Buck current limit
0h = 600 mA
1h = 150 mA
22-21BUCK_SELR/W1h Buck voltage selection
0h = Buck voltage is 3.3 V
1h = Buck voltage is 5.0 V
2h = Buck voltage is 4.0 V
3h = Buck voltage is 5.7 V
20RESERVEDR/W0h Reserved
19-0RESERVEDR/W0h Reserved