SLLSFQ3 January   2023 MCT8329A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Signal Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 120o Commutation
          1. 7.3.10.1.1 High-Side Modulation
          2. 7.3.10.1.2 Low-Side Modulation
          3. 7.3.10.1.3 Mixed Modulation
        2. 7.3.10.2 Variable Commutation
        3. 7.3.10.3 Lead Angle Control
        4. 7.3.10.4 Closed loop accelerate
      11. 7.3.11 Speed Loop
      12. 7.3.12 Power Loop
      13. 7.3.13 Anti-Voltage Surge (AVS)
      14. 7.3.14 Output PWM Switching Frequency
      15. 7.3.15 Fast Start-up (< 50 ms)
        1. 7.3.15.1 BEMF Threshold
        2. 7.3.15.2 Dynamic Degauss
      16. 7.3.16 Fast Deceleration
      17. 7.3.17 Dynamic Voltage Scaling
      18. 7.3.18 Motor Stop Options
        1. 7.3.18.1 Coast (Hi-Z) Mode
        2. 7.3.18.2 Recirculation Mode
        3. 7.3.18.3 Low-Side Braking
        4. 7.3.18.4 High-Side Braking
        5. 7.3.18.5 Active Spin-Down
      19. 7.3.19 FG Configuration
        1. 7.3.19.1 FG Output Frequency
        2. 7.3.19.2 FG in Open-Loop
        3. 7.3.19.3 FG During Motor Stop
        4. 7.3.19.4 FG Behaviour During Fault
      20. 7.3.20 Protections
        1. 7.3.20.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.20.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.20.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.20.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.20.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.20.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.20.7  Thermal Shutdown (OTSD)
        8. 7.3.20.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.20.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.20.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.20.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.20.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.20.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.20.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.20.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.20.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.20.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.20.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.20.10 Motor Lock (MTR_LCK)
          1. 7.3.20.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.20.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.20.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.20.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.20.11 Motor Lock Detection
          1. 7.3.20.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.20.11.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.20.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.20.12 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2. 8.2.2.2 120o and variable commutation
        3. 8.2.2.3 Faster startup time
        4. 8.2.2.4 Setting the BEMF threshold
        5. 8.2.2.5 Maximum speed
        6. 8.2.2.6 Faster deceleration
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8.1 Fault_Status Registers

#GUID-20220906-SS0T-66SF-MJTL-K7G1PDSBMVQR/FAULT_STATUS_FAULT_STATUS_TABLE_1_TABLE lists the memory-mapped registers for the Fault_Status registers. All register offset addresses not listed in #GUID-20220906-SS0T-66SF-MJTL-K7G1PDSBMVQR/FAULT_STATUS_FAULT_STATUS_TABLE_1_TABLE should be considered as reserved locations and the register contents should not be modified.

Table 7-42 FAULT_STATUS Registers
Offset Acronym Register Name Section
E0h GATE_DRIVER_FAULT_STATUS Fault Status Register GATE_DRIVER_FAULT_STATUS Register (Offset = E0h) [Reset = 00000000h]
E2h CONTROLLER_FAULT_STATUS Fault Status Register CONTROLLER_FAULT_STATUS Register (Offset = E2h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. #GUID-20220906-SS0T-66SF-MJTL-K7G1PDSBMVQR/FAULT_STATUS_FAULT_STATUS_LEGEND_TABLE shows the codes that are used for access types in this section.

Table 7-43 Fault_Status Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default value

7.8.1.1 GATE_DRIVER_FAULT_STATUS Register (Offset = E0h) [Reset = 00000000h]

GATE_DRIVER_FAULT_STATUS is shown in #GUID-20220906-SS0T-66SF-MJTL-K7G1PDSBMVQR/FAULT_STATUS_FAULT_STATUS_FAULT_STATUS_GATE_DRIVER_FAULT_STATUS_TABLE_TABLE.

Return to the Summary Table.

Status of various faults

Table 7-44 GATE_DRIVER_FAULT_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 DRIVER_FAULT R 0h Logic OR of driver fault registers
0h = No Gate Driver fault condition is detected
1h = Gate Driver fault condition is detected
30 PWR_ON R 0h Power On Detection
0h = Powerup condition is detected
1h = Powerup condition is cleared
29 RESERVED R 0h Reserved
28 OCP_VDS_FAULT R 0h Overcurrent VDS Fault status
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
27 OCP_SNS_FAULT R 0h Overcurrent Sense Fault status
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
26 BST_UV_FAULT R 0h Boot Strap UV protection status
0h = No BST undervoltage condition is detected on VM
1h = BST undervoltage condition is detected on VM
25 GVDD_UV_FLT R 0h GVDD UV fault status
0h = No GVDD undervoltage condition is detected on VM
1h = GVDD undervoltage condition is detected on VM
24 DRV_OFF R 0h Supply overvoltage protection status
0h = DRV is ON
1h = DRVOff state detected
23-0 RESERVED R 0h Reserved

7.8.1.2 CONTROLLER_FAULT_STATUS Register (Offset = E2h) [Reset = 00000000h]

CONTROLLER_FAULT_STATUS is shown in #GUID-20220906-SS0T-66SF-MJTL-K7G1PDSBMVQR/FAULT_STATUS_FAULT_STATUS_FAULT_STATUS_CONTROLLER_FAULT_STATUS_TABLE_TABLE.

Return to the Summary Table.

Status of various faults

Table 7-45 CONTROLLER_FAULT_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 CONTROLLER_FAULT R 0h Logic OR of controller fault registers
0h = No controller fault condition is detected
1h = Controller fault condition is detected
30 RESERVED R 0h Reserved
29 IPD_FREQ_FAULT R 0h Indicates IPD frequency fault
0h = No IPD frequency fault detected
1h = IPD frequency fault detected
28 IPD_T1_FAULT R 0h Indicates IPD T1 fault
0h = No IPD T1 fault detected
1h = IPD T1 fault detected
27 RESERVED R 0h Reserved
26-24 RESERVED R 0h Reserved
23 ABN_SPEED R 0h Indicates abnormal speed motor lock condition
0h = No abnormal speed fault detected
1h = Abnormal Speed fault detected
22 LOSS_OF_SYNC R 0h Indicates sync lost motor lock condition
0h = No sync lost fault detected
1h = Sync lost fault detected
21 NO_MTR R 0h Indicates no motor fault
0h = No motor fault not detected
1h = No motor fault detected
20 MTR_LCK R 0h Indicates when one of the motor lock is triggered
0h = Motor lock fault not detected
1h = Motor lock fault detected
19 CBC_ILIMIT R 0h Indicates CBC current limit fault
0h = No CBC fault detected
1h = CBC fault detected
18 LOCK_ILIMIT R 0h Indicates lock detection current limit fault
0h = No lock current limit fault detected
1h = Lock current limit fault detected
17 MTR_UNDER_VOLTAGE R 0h Indicates motor undervoltage fault
0h = No motor undervoltag detected
1h = Motor undervoltage detected
16 MTR_OVER_VOLTAGE R 0h Indicates motor overvoltage fault
0h = No motor overvoltage detected
1h = Motor overvoltage detected
15 RESERVED R 0h Reserved
14-3 RESERVED R 0h Reserved
2 STL_EN R 0h Indicates STL is enabled in EEPROM
0h = STL Disable
1h = STL Enable
1 STL_STATUS R 0h Indicates STL success criteria Pass = 1b; Fail = 0b
0h = STL Fail
1h = STL Pass
0 APP_RESET R 0h App reset
0h = App Reset Fail
1h = App Reset Succesfull