SLLSFQ3 January   2023 MCT8329A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Signal Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 120o Commutation
          1. 7.3.10.1.1 High-Side Modulation
          2. 7.3.10.1.2 Low-Side Modulation
          3. 7.3.10.1.3 Mixed Modulation
        2. 7.3.10.2 Variable Commutation
        3. 7.3.10.3 Lead Angle Control
        4. 7.3.10.4 Closed loop accelerate
      11. 7.3.11 Speed Loop
      12. 7.3.12 Power Loop
      13. 7.3.13 Anti-Voltage Surge (AVS)
      14. 7.3.14 Output PWM Switching Frequency
      15. 7.3.15 Fast Start-up (< 50 ms)
        1. 7.3.15.1 BEMF Threshold
        2. 7.3.15.2 Dynamic Degauss
      16. 7.3.16 Fast Deceleration
      17. 7.3.17 Dynamic Voltage Scaling
      18. 7.3.18 Motor Stop Options
        1. 7.3.18.1 Coast (Hi-Z) Mode
        2. 7.3.18.2 Recirculation Mode
        3. 7.3.18.3 Low-Side Braking
        4. 7.3.18.4 High-Side Braking
        5. 7.3.18.5 Active Spin-Down
      19. 7.3.19 FG Configuration
        1. 7.3.19.1 FG Output Frequency
        2. 7.3.19.2 FG in Open-Loop
        3. 7.3.19.3 FG During Motor Stop
        4. 7.3.19.4 FG Behaviour During Fault
      20. 7.3.20 Protections
        1. 7.3.20.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.20.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.20.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.20.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.20.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.20.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.20.7  Thermal Shutdown (OTSD)
        8. 7.3.20.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.20.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.20.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.20.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.20.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.20.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.20.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.20.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.20.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.20.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.20.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.20.10 Motor Lock (MTR_LCK)
          1. 7.3.20.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.20.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.20.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.20.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.20.11 Motor Lock Detection
          1. 7.3.20.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.20.11.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.20.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.20.12 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2. 8.2.2.2 120o and variable commutation
        3. 8.2.2.3 Faster startup time
        4. 8.2.2.4 Setting the BEMF threshold
        5. 8.2.2.5 Maximum speed
        6. 8.2.2.6 Faster deceleration
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (PVDD, GVDD, AVDD, DVDD, VREG, GCTRL)
IPVDDQ PVDD sleep mode current VPVDD = 24V, VSPEED/WAKE = 0, TA = 25 °C,  AVDD connected to VREG 3 5 µA
VSPEED/WAKE = 0, TA = 125 °C,  AVDD connected to VREG 3.5 6 µA
IPVDDS PVDD standby mode current VPVDD = 24 V,  VSPEED/WAKE < VEN_SB, DRVOFF = LOW, TA = 25 °C,  AVDD connected to VREG 25 28 mA
VSPEED/WAKE < VEN_SB, DRVOFF = LOW,  AVDD connected to VREG 25 28 mA
IPVDD PVDD active mode current VPVDD = 24 V, VSPEED/WAKE > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), TJ = 25 °C, No FETs and motor connected, AVDD connected to VREG 28 30 mA
VPVDD = 24 V, VSPEED/WAKE > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), No FETs and motor connected, AVDD connected to VREG 28 30 mA
VPVDD = 8 V, VSPEED/WAKE > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), TJ = 25 °C, No FETs and motor connected, AVDD not connected to VREG, VREG = 3.3V external 8.5 14.1 mA
VPVDD = 24 V, VSPEED/WAKE > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), No FETs and motor connected, AVDD not connected to VREG, VREG = 3.3V external 8.5 11.1 mA
IVREG VREG pin active mode current VSPEED/WAKE > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), VREG connected to AVDD 25 mA
ILBSx Bootstrap pin leakage current VBSTx = VSHx = 60V, VGVDD = 0V, VSPEED/WAKE = LOW 5 10 16 µA
ILBS_TRAN Bootstrap pin active mode transient leakage current  GLx = GHx = Switching at 20kHz, No FETs connected 60 115 300 µA
VGVDD_RT GVDD Gate driver regulator voltage (Room Temperature) VPVDD ≥ 40 V, IGS  = 10 mA, TJ= 25°C 11.8 13 15 V
22 V ≤VPVDD ≤ 40 V, IGS  = 30 mA, TJ= 25°C 11.8 13 15 V
8 V ≤VPVDD ≤ 22 V, IGS  = 30 mA, TJ= 25°C 11.8 13 15 V
6.75 V ≤VPVDD ≤ 8 V, IGS  = 10 mA, TJ= 25°C 11.8 13 14.5 V
4.5 V ≤VPVDD ≤ 6.75 V, IGS  = 10 mA, TJ= 25°C 2*VPVDD - 1 13.5 V
VGVDD GVDD Gate driver regulator voltage  VPVDD ≥ 40 V, IGS  = 10 mA 11.5 15.5 V
22 V ≤VPVDD ≤ 40 V, IGS  = 30 mA 11.5 15.5 V
8 V ≤VPVDD ≤ 22 V; IGS  = 30 mA 11.5 15.5 V
6.75 V ≤VPVDD ≤ 8 V, IGS  = 10 mA 11.5 14.5 V
4.5 V ≤VPVDD ≤ 6.75 V, IGS  = 10 mA 2*VPVDD - 1.4 13.5 V
VAVDD_RT AVDD Analog regulator voltage (Room Temperature) VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 30 mA, TJ= 25°C 3.26 3.3 3.33 V
VPVDD ≥ 6 V, 30 mA ≤ IAVDD ≤ 80 mA, TJ= 25°C 3.2 3.3 3.4 V
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA, TJ= 25°C 3.13 3.3 3.46 V
VDVDD Digital regulator voltage  VREG = 3.3V 1.4 1.55 1.65 V
VAVDD AVDD Analog regulator voltage VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 80 mA  3.2 3.3 3.4 V
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA 3.125 3.3 3.5 V
VGCTRL Gate control volatge VPVDD  > 4.5 V 4.9 5.7 6.5 V
GATE DRIVERS (GHx, GLx, SHx, SLx)
VGSHx_LO High-side gate drive low level voltage IGHx = -100 mA; VGVDD = 12V; No FETs connected 0.05 0.11 0.24 V
VGSHx_HI High-side gate drive high level voltage (VBSTx - VGHx) IGHx = 100 mA; VGVDD = 12V; No FETs connected 0.28 0.44 0.82 V
VGSLx_LO Low-side gate drive low level voltage IGLx = -100 mA; VGVDD = 12V; No FETs connected 0.05 0.11 0.27 V
VGSLx_HI Low-side gate drive high level voltage (VGVDD - VGLx) IGLx = 100 mA; VGVDD = 12V; No FETs connected 0.28 0.44 0.82 V
RDS(ON)_PU_HS High-side pullup switch resistance IGHx = 100 mA; VGVDD= 12V 2.7 4.5 8.4 Ω
RDS(ON)_PD_HS High-side pulldown switch resistance IGHx = 100 mA; VGVDD = 12V 0.5 1.1 2.4 Ω
RDS(ON)_PU_LS Low-side pullup switch resistance IGLx = 100 mA; VGVDD = 12V 2.7 4.5 8.3 Ω
RDS(ON)_PD_LS Low-side pulldown switch resistance IGLx = 100 mA; VGVDD = 12V 0.5 1.1 2.8 Ω
IDRIVEP_HS High-side peak source gate current VGSHx = 12V 550 1000 1575 mA
IDRIVEN_HS High-side peak sink gate current VGSHx = 0V 1150 2000 2675 mA
IDRIVEP_LS Low-side peak source gate current VGSLx = 12V 550 1000 1575 mA
IDRIVEN_LS Low-side peak sink gate current VGSLx = 0V 1150 2000 2675 mA
RPD_LS Low-side passive pull down GLx to LSS 80 100 120 kΩ
RPDSA_HS High-side semiactive pull down GHx to SHx, VGSHx = 2V 8 10 12.5 kΩ
BOOTSTRAP DIODES
VBOOTD Bootstrap diode forward voltage IBOOT = 100 µA 0.8 V
IBOOT = 100 mA 1.6 V
RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 50 mA 4.5 5.5 9 Ω
LOGIC-LEVEL INPUTS (BRAKE, DIR, EXT_CLK, SCL, SDA, SPEED/WAKE)
VIL Input logic low voltage AVDD = 3 to 3.6 V 0.25*AVDD V
VIH Input logic high voltage AVDD = 3 to 3.6 V 0.65*AVDD V
VHYS Input hysteresis 50 500 800 mV
IIL Input logic low current AVDD = 3 to 3.6 V -0.15 0.15 µA
IIH Input logic high current AVDD = 3 to 3.6 V -0.3 0.1 µA
RPD_SPEED Input pulldown resistance SPEED/WAKE pin To GND 0.6 1 1.4 MΩ
LOGIC-LEVEL INPUTS (DRVOFF)
VIL Input logic low voltage 0.8 V
VIH Input logic high voltage 2.2 V
VHYS Input hysteresis 200 400 650 mV
IIL Input logic low current Pin Voltage = 0 V; -1 0 1 µA
IIH Input logic high current Pin Voltage = 5 V; 7 20 35 µA
RPD_DRVOFF Input pulldown resistance DRVOFF To GND 100 200 300 kΩ
OPEN-DRAIN OUTPUTS (nFAULT, FG)
VOL Output logic low voltage IOD =-5 mA 0.4 V
IOZ Output logic high current VOD = 3.3 V 0 0.5 µA
SPEED INPUT - ANALOG MODE
VANA_FS Analog full-speed voltage 2.95 3 3.05 V
VANA_RES Analog voltage resolution 732 μV
SPEED INPUT - PWM MODE
ƒPWM PWM input frequency 0.01 95 kHz
ResPWM PWM input resolution fPWM = 0.01 to 0.35 kHz 11 12 13 bits
fPWM = 0.35 to 2 kHz 12 13 14 bits
fPWM = 2 to 3.5 kHz 11 11.5 12 bits
fPWM = 3.5 to 7 kHz 13 13.5 14 bits
fPWM = 7 to 14 kHz 12 12.5 13 bits
fPWM = 14 to 29.2 kHz 11 11.5 12 bits
fPWM = 29.3 to 60 kHz 10 10.5 11 bits
fPWM = 60 to 95 kHz 8 9 10 bits
SPEED INPUT - FREQUENCY MODE
ƒPWM_FREQ PWM input frequency range Duty cycle = 50% 3 32767 Hz
SLEEP MODE
VEN_SL Analog voltage to enter sleep mode SPD_CTRL_MODE = 00b (analog mode) 40 mV
VEX_SL Analog voltage to exit sleep mode 2.6 V
tDET_ANA Time needed to detect wake up signal on SPEED/WAKE pin SPD_CTRL_MODE = 00b (analog mode), VSPEED/WAKE > VEX_SL 0.5 1 1.5 μs
tWAKE Wakeup time from sleep mode VSPEED/WAKE > VEX_SL to DVDD voltage available, SPD_CTRL_MODE = 00b (analog mode) 3 5 ms
tEX_SL_DR_ANA Time taken to drive motor after exiting from sleep mode SPD_CTRL_MODE = 00b (analog mode)
VSPEED/WAKE > VEX_SL, ISD detection disabled		 30 ms
tDET_PWM Time needed to detect wake up signal on SPEED pin SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED/WAKE > VIH		 0.5 1 1.5 μs
tWAKE_PWM Wakeup time from sleep mode VSPEED/WAKE > VIH to DVDD voltage available and release nFault, SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode) 3 5 ms
tEX_SL_DR_PWM Time taken to drive motor after wakeup from sleep state SPD_CTRL_MODE = 01b (PWM mode)
VSPEED/WAKE > VIH, ISD detection disabled		 30 ms
tDET_SL_ANA Time needed to detect sleep command SPD_CTRL_MODE = 00b (analog mode)
VSPEED/WAKE < VEN_SL,  SLEEP_TIME = 00b or 01b		 0.5 1 2 ms
tDET_SL_PWM Time needed to detect sleep command SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode), VSPEED/WAKE < VIL(PWM mode and Frequency mode), SLEEP_TIME = 00b 0.035 0.05 0.065 ms
SPD_CTRL_MODE = 01b (PWM mode),  or 11b (Frequency mode), VSPEED/WAKE < VIL(PWM mode and Frequency mode), SLEEP_TIME = 01b 0.14 0.2 0.26 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode) or 00b (analog mode), VSPEED/WAKE < VIL(PWM mode and Frequency mode), VSPEED/WAKE < VEN_SL (analog mode), SLEEP_TIME = 10b 14 20 26 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode) or 00b (analog mode), VSPEED/WAKE < VIL(PWM mode and Frequency mode), VSPEED/WAKE < VEN_SL (analog mode), SLEEP_TIME = 11b 140 200 260 ms
tEN_SL Time needed to stop driving motor after detecting sleep command VSPEED/WAKE < VEN_SL (analog mode) or VSPEED/WAKE < VIL (PWM and frequency mode) 1 2 ms
STANDBY MODE
tEX_SB_DR_ANA Time taken to drive motor after exiting standby mode SPD_CTRL_MODE = 00b (analog mode)
VSPEED > VEN_SB, ISD detection disabled		 6 ms
tEX_SB_DR_PWM Time taken to drive motor after exiting standby mode SPD_CTRL_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled		 6 ms
tDET_SB_ANA Time needed to detect standby mode SPD_CTRL_MODE = 00b (analog mode)
VSPEED < VEN_SB		 0.5 1 2 ms
tEN_SB_PWM Time needed to detect standby command SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 00b		 0.035 0.05 0.065 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 01b		 0.14 0.2 0.26 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 10b		 14 20 26 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 11b		 140 200 260 ms
tEN_SB_DIG Time needed to detect standby mode SPD_CTRL_MODE = 10b (I2C mode), SPEED_CMD = 0 1 2 ms
tEN_SB Time needed to stop driving motor after detecting standby command VSPEED < VEN_SL (analog mode) or VSPEED < VIL (PWM mode) or SPEED command = 0 (I2C mode) 1 2 ms
OSCILLATOR
SLACC Speed loop accuracy TJ = -25 to 125 oC . -2.25 2.25 %
fOSCREF External clock reference EXT_CLK_CONFIG = 000b 8 kHz
EXT_CLK_CONFIG = 001b 16 kHz
EXT_CLK_CONFIG = 010b 32 kHz
EXT_CLK_CONFIG = 011b 64 kHz
EXT_CLK_CONFIG = 100b 128 kHz
EXT_CLK_CONFIG = 101b 256 kHz
EXT_CLK_CONFIG = 110b 512 kHz
EXT_CLK_CONFIG = 111b 1024 kHz
PROTECTION CIRCUITS
VVREG_UVLO Regulator input undervoltage lockout (VREG-UVLO) Supply rising 1.8 1.9 2 V
Supply falling 1.7 1.8 1.9 V
VVREG_UVLO_HYS Regulator UVLO hysteresis Rising to falling threshold 30 100 160 mV
tVREG_UVLO_DEG Regulator UVLO deglitch time 5 µs
VDVDD_UVLO Digital regulator undervoltage lockout (DVDD-UVLO) Supply rising 1.2 1.25 1.32 V
VDVDD_UVLO Digital regulator undervoltage lockout (DVDD-UVLO) Supply falling 1.25 1.35 1.45 V
VPVDD_UV PVDD undervoltage lockout threshold VPVDD rising 4.3 4.4 4.5 V
VPVDD falling 4 4.1 4.25
VPVDD_UV_HYS PVDD undervoltagelockout  hysteresis Rising to falling threshold 225 265 325 mV
tPVDD_UV_DG PVDD undervoltage deglitch time 10 20 30 µs
VAVDD_POR AVDD supply POR threshold AVDD rising 2.7 2.85 3.0 V
AVDD falling 2.5 2.65 2.8
VAVDD_POR_HYS AVDD POR hysteresis Rising to falling threshold 170 200 250 mV
tAVDD_POR_DG AVDD POR deglitch time 7 12 22 µs
VGVDD_UV GVDD undervoltage threshold VGVDD rising 7.3 7.5 7.8 V
VGVDD falling 6.4 6.7 6.9 V
VGVDD_UV_HYS GVDD undervoltage hysteresis Rising to falling threshold 800 900 1000 mV
tGVDD_UV_DG GVDD undervoltage deglitch time 5 10 15 µs
VBST_UV Bootstrap undervoltage threshold VBSTx- VSHx; VBSTx rising 3.9 4.45 5 V
VBSTx- VSHx; VBSTx falling 3.7 4.2 4.8 V
VBST_UV_HYS Bootstrap undervoltage hysteresis Rising to falling threshold 150 220 285 mV
tBST_UV_DG Bootstrap undervoltage deglitch time 2 4 6 µs
VDS_LVL VDS overcurrent protection threshold Reference  SEL_VDS_LVL = 0000 0.04 0.06 0.08 V
SEL_VDS_LVL = 0001 0.09 0.12 0.15 V
SEL_VDS_LVL = 0010 0.14 0.18 0.23 V
SEL_VDS_LVL = 0011 0.19 0.24 0.29 V
SEL_VDS_LVL = 0100 0.23 0.3 0.37 V
SEL_VDS_LVL = 0101 0.3 0.36 0.43 V
SEL_VDS_LVL = 0110 0.35 0.42 0.5 V
SEL_VDS_LVL = 0111 0.4 0.48 0.56 V
SEL_VDS_LVL = 1000 0.5 0.6 0.7 V
SEL_VDS_LVL = 1001 0.65 0.8 0.9 V
SEL_VDS_LVL = 1010 0.85 1 1.15 V
SEL_VDS_LVL = 1011 1 1.2 1.34 V
SEL_VDS_LVL = 1100 1.2 1.4 1.58 V
SEL_VDS_LVL = 1101 1.4 1.6 1.78 V
SEL_VDS_LVL = 1110 1.6 1.8 2 V
SEL_VDS_LVL = 1111 1.7 2 2.2 V
VSENSE_LVL VSENSE overcurrent protection threshold LSS to GND pin = 0.5V 0.48 0.5 0.52 V
tDS_BLK VDS overcurrent protection blanking time  0.5 1 2.7 µs
tDS_DG VDS and VSENSE overcurrent protection deglitch time  1.5 3 5 µs
tSD_SINK_DIG DRVOFF peak sink current duration 3 5 7 µs
tSD_DIG DRVOFF digital shutdown delay 0.5 1.5 2.2 µs
tSD DRVOFF analog shutdown delay 7 14 21 µs
TOTSD Thermal shutdown temperature TJ rising;   160 170 187 °C
THYS Thermal shutdown hysteresis 16 20 23 °C
I2C Serial Interface
VI2C_L LOW-level input voltage -0.5 0.3*AVDD V
VI2C_H HIGH-level input voltage 0.7*AVDD 5.5 V
VI2C_HYS Hysterisis 0.05*AVDD V
VI2C_OL LOW-level output voltage open-drain at 2mA sink current 0 0.4 V
II2C_OL LOW-level output current VI2C_OL = 0.6V 6 mA
II2C_IL Input current on SDA and SCL -10(1) 10(1) µA
Ci Capacitance for SDA and SCL 10 pF
tof Output fall time from VI2C_H(min) to VI2C_L(max) Standard Mode 250(2) ns
Fast Mode 250(2) ns
tSP Pulse width of spikes that must be suppressed by the input filter Fast Mode 0 50(3) ns
EEPROM
EEProg Programing voltage 1.35 1.5 1.65 V
EERET Retention TA = 25 ℃ 100 Years
TJ = -40 to 150 ℃ 10 Years
EEEND Endurance TJ = -40 to 150 ℃ 1000 Cycles
TJ = -40 to 85 ℃ 20000 Cycles
(1) If AVDD is switched off, I/O pins must not obstruct the SDA and SCL lines.
(2) The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
(3) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns