SLAS703B April   2010  – August 2015 MSP430BT5190

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Characteristics
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Inputs - Ports P1 and P2
    9. 5.9  Leakage Current - General-Purpose I/O
    10. 5.10 Outputs - General-Purpose I/O (Full Drive Strength)
    11. 5.11 Outputs - General-Purpose I/O (Reduced Drive Strength)
    12. 5.12 Output Frequency - General-Purpose I/O
    13. 5.13 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2
    18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20 DCO Frequency
    21. 5.21 PMM, Brown-Out Reset (BOR)
    22. 5.22 PMM, Core Voltage
    23. 5.23 PMM, SVS High Side
    24. 5.24 PMM, SVM High Side
    25. 5.25 PMM, SVS Low Side
    26. 5.26 PMM, SVM Low Side
    27. 5.27 Wake-up Times From Low-Power Modes and Reset
    28. 5.28 Timer_A
    29. 5.29 Timer_B
    30. 5.30 USCI (UART Mode), Recommended Operating Conditions
    31. 5.31 USCI (UART Mode)
    32. 5.32 USCI (SPI Master Mode), Recommended Operating Conditions
    33. 5.33 USCI (SPI Master Mode)
    34. 5.34 USCI (SPI Slave Mode)
    35. 5.35 USCI (I2C Mode)
    36. 5.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 5.37 12-Bit ADC, Timing Parameters
    38. 5.38 12-Bit ADC, Linearity Parameters
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootstrap Loader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Power-Management Module (PMM)
      4. 6.9.4  Hardware Multiplier (MPY)
      5. 6.9.5  Real-Time Clock (RTC_A)
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TA1
      12. 6.9.12 TB0
      13. 6.9.13 ADC12_A
      14. 6.9.14 CRC16
      15. 6.9.15 REF Voltage Reference
      16. 6.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
      18. 6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      19. 6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Experimenter Boards
          2. 7.1.2.2.2 Debugging and Programming Tools
          3. 7.1.2.2.3 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 TI-RTOS
          4. 7.1.2.3.4 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Export Control Notice
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Revision History

Changes from August 5, 2013 to August 6, 2015

  • Document format and organization changes throughout, including addition of section numbering Go
  • Added Device Information tableGo
  • Moved functional block diagram to Figure 1-1, Functional Block DiagramGo
  • Added Section 3, Device Characteristics, and moved Table 3-1 to itGo
  • Added signal names to ZQW pinoutGo
  • Added Section 5, Specifications, and moved all electrical and timing specifications to itGo
  • Added Section 5.2, ESD RatingsGo
  • Added note to CVCOREGo
  • Moved Section 5.6, Thermal CharacteristicsGo
  • Changed the TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pFGo
  • Corrected spelling of MRG bits in symbol and description for fMCLK,MRG parameterGo
  • Corrected spelling of NMIIFG in Table 6-6, System Module Interrupt Vector RegistersGo
  • Changed P5.3 schematic (added P5SEL.2 and XT2BYPASS inputs with AND and OR gates)Go
  • Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rowsGo
  • Changed P7.1 schematic (added P7SEL.1 input and OR gate)Go
  • Changed P7SEL.1 column from X to 0 for "P7.1 (I/O)" rowsGo
  • Added Section 7 and moved Tools Support, Device Nomenclature, ESD Caution, and Trademarks sections to itGo
  • Added Section 8Go