SLAS703B April   2010  – August 2015 MSP430BT5190

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Characteristics
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Inputs - Ports P1 and P2
    9. 5.9  Leakage Current - General-Purpose I/O
    10. 5.10 Outputs - General-Purpose I/O (Full Drive Strength)
    11. 5.11 Outputs - General-Purpose I/O (Reduced Drive Strength)
    12. 5.12 Output Frequency - General-Purpose I/O
    13. 5.13 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2
    18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20 DCO Frequency
    21. 5.21 PMM, Brown-Out Reset (BOR)
    22. 5.22 PMM, Core Voltage
    23. 5.23 PMM, SVS High Side
    24. 5.24 PMM, SVM High Side
    25. 5.25 PMM, SVS Low Side
    26. 5.26 PMM, SVM Low Side
    27. 5.27 Wake-up Times From Low-Power Modes and Reset
    28. 5.28 Timer_A
    29. 5.29 Timer_B
    30. 5.30 USCI (UART Mode), Recommended Operating Conditions
    31. 5.31 USCI (UART Mode)
    32. 5.32 USCI (SPI Master Mode), Recommended Operating Conditions
    33. 5.33 USCI (SPI Master Mode)
    34. 5.34 USCI (SPI Slave Mode)
    35. 5.35 USCI (I2C Mode)
    36. 5.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 5.37 12-Bit ADC, Timing Parameters
    38. 5.38 12-Bit ADC, Linearity Parameters
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootstrap Loader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Power-Management Module (PMM)
      4. 6.9.4  Hardware Multiplier (MPY)
      5. 6.9.5  Real-Time Clock (RTC_A)
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TA1
      12. 6.9.12 TB0
      13. 6.9.13 ADC12_A
      14. 6.9.14 CRC16
      15. 6.9.15 REF Voltage Reference
      16. 6.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
      18. 6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      19. 6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Experimenter Boards
          2. 7.1.2.2.2 Debugging and Programming Tools
          3. 7.1.2.2.3 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 TI-RTOS
          4. 7.1.2.3.4 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Export Control Notice
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage applied at VCC to VSS –0.3 4.1 V
Voltage applied to any pin (excluding VCORE)(2) –0.3 VCC + 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, Tstg(3) –55 105 °C
Maximum junction temperature, TJ 95 °C
(1) Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage during program execution and flash programming
(AVCC = DVCC1/2/3/4 = DVCC)(1)(2)
1.8 3.6 V
VSS Supply voltage (AVSS = DVSS1/2/3/4 = DVSS) 0 V
TA Operating free-air temperature I version –40 85 °C
TJ Operating junction temperature I version –40 85 °C
CVCORE Recommended capacitor at VCORE(3) 470 nF
CDVCC/CVCORE Capacitor ratio of DVCC to VCORE 10
fSYSTEM Processor frequency (maximum MCLK frequency)(4)(5) (see Figure 5-1) PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V 0 8.0 MHz
PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V 0 12.0
PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V 0 20.0
PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V 0 25.0
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.23 threshold parameters for the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
MSP430BT5190 slas703-op_cond.gifFigure 5-1 Frequency vs Supply Voltage

5.4 Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3)
PARAMETER EXECUTION MEMORY VCC PMMCOREVx FREQUENCY (fDCO = fMCLK = fSMCLK) UNIT
1 MHz 8 MHz 12 MHz 20 MHz 25 MHz
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
IAM, Flash Flash 3 V 0 0.29 0.33 1.84 2.08 mA
1 0.32 2.08 3.10
2 0.33 2.24 3.50 6.37
3 0.35 2.36 3.70 6.75 8.90 9.60
IAM, RAM RAM 3 V 0 0.17 0.19 0.88 0.99 mA
1 0.18 1.00 1.47
2 0.19 1.13 1.68 2.82
3 0.20 1.20 1.78 3.00 4.50 4.90
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
ILPM0,1MHz Low-power
mode 0(3)(9)
2.2 V 0 69 93 69 93 69 93 69 93 µA
3 V 3 73 100 73 100 73 100 73 100
ILPM2 Low-power
mode 2(4)(9)
2.2 V 0 11 15.5 11 15.5 11 15.5 11 15.5 µA
3 V 3 11.7 17.5 11.7 17.5 11.7 17.5 11.7 17.5
ILPM3,XT1LF Low-power mode 3, crystal mode(5)(9) 2.2 V 0 1.4 1.7 2.6 6.6 µA
1 1.5 1.8 2.9 9.9
2 1.5 2.0 3.3 10.1
3 V 0 1.8 2.1 2.4 2.8 7.1 13.6
1 1.8 2.3 3.1 10.5
2 1.9 2.4 3.5 10.6
3 2.0 2.3 2.6 3.9 11.8 14.8
ILPM3,VLO Low-power mode 3, VLO mode(6)(9) 3 V 0 1.0 1.2 1.42 2.0 5.8 12.9 µA
1 1.0 1.3 2.3 6.0
2 1.1 1.4 2.8 6.2
3 1.2 1.4 1.62 3.0 6.2 13.9
ILPM4 Low-power
mode 4(7)(9)
3 V 0 1.1 1.2 1.35 1.9 5.7 12.9 µA
1 1.2 1.2 2.2 5.9
2 1.3 1.3 2.6 6.1
3 1.3 1.3 1.52 2.9 6.2 13.9
ILPM4.5 Low-power mode 4.5(8) 3 V 0.10 0.10 0.13 0.20 0.50 1.14 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1 MHz operation, DCO bias generator enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK =  fMCLK = fSMCLK = 0 MHz
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK =  fMCLK = fSMCLK = 0 MHz
(9) Current for brownout, high side supervisor (SVSH) normal mode included. Low-side supervisor and monitors disabled (SVSL, SVML). High side monitor disabled (SVMH). RAM retention enabled.

5.6 Thermal Characteristics

VALUE UNIT
θJA Junction-to-ambient thermal resistance, still air Low-K board (JESD51-3) QFP (PZ) 50.1 °C/W
BGA (ZQW) 60
High-K board (JESD51-7) QFP (PZ) 40.8
BGA (ZQW) 42
θJC Junction-to-case thermal resistance QFP (PZ) 8.9 °C/W
BGA (ZQW) 8

5.7 Schmitt-Trigger Inputs – General-Purpose I/O(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage 1.8 V 0.80 1.40 V
3 V 1.50 2.10
VIT– Negative-going input threshold voltage 1.8 V 0.45 1.00 V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ – VIT–) 1.8 V 0.3 0.85 V
3 V 0.4 1.0
RPull Pullup or pulldown resistor(2) For pullup: VIN = VSS
For pulldown: VIN = VCC
20 35 50
CI Input capacitance VIN = VSS or VCC 5 pF
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when the pullup or pulldown resistor is enabled.

5.8 Inputs – Ports P1 and P2(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
t(int) External interrupt timing(2) Port P1, P2: P1.x to P2.x, external trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int).

5.9 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.y) High-impedance leakage current  (1)(2) 1.8 V, 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled.

5.10 Outputs – General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage I(OHmax) = –3 mA(1) 1.8 V VCC – 0.25 VCC V
I(OHmax) = –10 mA(2) VCC – 0.60 VCC
I(OHmax) = –5 mA(1) 3 V VCC – 0.25 VCC
I(OHmax) = –15 mA(2) VCC – 0.60 VCC
VOL Low-level output voltage I(OLmax) = 3 mA(1) 1.8 V VSS VSS + 0.25 V
I(OLmax) = 10 mA(2) VSS VSS + 0.60
I(OLmax) = 5 mA(1) 3 V VSS VSS + 0.25
I(OLmax) = 15 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.

5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage I(OHmax) = –1 mA(1) 1.8 V VCC – 0.25 VCC V
I(OHmax) = –3 mA(2) VCC – 0.60 VCC
I(OHmax) = –2 mA(1) 3 V VCC – 0.25 VCC
I(OHmax) = –6 mA(2) VCC – 0.60 VCC
VOL Low-level output voltage I(OLmax) = 1 mA(1) 1.8 V VSS VSS + 0.25 V
I(OLmax) = 3 mA(2) VSS VSS + 0.60
I(OLmax) = 2 mA(1) 3 V VSS VSS + 0.25
I(OLmax) = 6 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
(3) Selecting reduced drive strength may reduce EMI.

5.12 Output Frequency – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fPx.y Port output frequency (with load) P1.6/SMCLK (1)(2) VCC = 1.8 V
PMMCOREVx = 0
16 MHz
VCC = 3 V
PMMCOREVx = 3
25
fPort_CLK Clock output frequency P1.0/TA0CLK/ACLK
P1.6/SMCLK
P2.0/TA1CLK/MCLK
CL = 20 pF(2)
VCC = 1.8 V
PMMCOREVx = 0
16 MHz
VCC = 3 V
PMMCOREVx = 3
25
(1) A resistive divider with 2 × R1  between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

MSP430BT5190 slas703-005.gifFigure 5-2 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430BT5190 slas703-007.gifFigure 5-4 Typical High-Level Output Current vs High-Level Output Voltage
MSP430BT5190 slas703-006.gifFigure 5-3 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430BT5190 slas703-008.gifFigure 5-5 Typical High-Level Output Current vs High-Level Output Voltage

5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

MSP430BT5190 slas703-009.gifFigure 5-6 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430BT5190 slas703-011.gifFigure 5-8 Typical High-Level Output Current vs High-Level Output Voltage
MSP430BT5190 slas703-010.gifFigure 5-7 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430BT5190 slas703-012.gifFigure 5-9 Typical High-Level Output Current vs High-Level Output Voltage

5.15 Crystal Oscillator, XT1, Low-Frequency Mode(5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
ΔIDVCC.LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
3 V 0.075 µA
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
0.170
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
0.290
fXT1,LF0 XT1 oscillator crystal frequency, LF mode XTS = 0, XT1BYPASS = 0 32768 Hz
fXT1,LF,SW XT1 oscillator logic-level square-wave input frequency, LF mode XTS = 0, XT1BYPASS = 1(6)(7) 10 32.768 50 kHz
OALF Oscillation allowance for LF crystals(8) XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
CL,eff Integrated effective load capacitance, LF mode(1) XTS = 0, XCAPx = 0(2) 1 pF
XTS = 0, XCAPx = 1 5.5
XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 12.0
Duty cycle, LF mode XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
30% 70%
fFault,LF Oscillator fault frequency, LF mode(4) XTS = 0(3) 10 10000 Hz
tSTART,LF Start-up time, LF mode fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
3 V 1000 ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
500
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag.
(5) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
  • Keep the trace between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
  • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
  • Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT1BYPASS is set, XT1 circuits are automatically powered down. The input signal must be a digital square wave with the parametrics defined in the Schmitt-Trigger Inputs section.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application:
  • For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
  • For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
  • For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
  • For XT1DRIVEx = 3, CL,eff ≥ 6 pF.

5.16 Crystal Oscillator, XT1, High-Frequency Mode(5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IDVCC.HF XT1 oscillator crystal current, HF mode fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C
3 V 200 µA
fOSC = 12 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
325
fOSC = 32 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
450
fXT1,HF0 XT1 oscillator crystal frequency, HF mode 0 XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0(7)
4 8 MHz
fXT1,HF1 XT1 oscillator crystal frequency, HF mode 1 XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1(7)
8 16 MHz
fXT1,HF2 XT1 oscillator crystal frequency, HF mode 2 XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2(7)
16 24 MHz
fXT1,HF3 XT1 oscillator crystal frequency, HF mode 3 XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3(7)
24 32 MHz
fXT1,HF,SW XT1 oscillator logic-level square-wave input frequency, HF mode, bypass mode XTS = 1,
XT1BYPASS = 1(6)(7)
1.5 32 MHz
OAHF Oscillation allowance for HF crystals(8) XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,HF = 6 MHz, CL,eff = 15 pF
450 Ω
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,HF = 12 MHz, CL,eff = 15 pF
320
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
fXT1,HF = 20 MHz, CL,eff = 15 pF
200
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3,
fXT1,HF = 32 MHz, CL,eff = 15 pF
200
tSTART,HF Start-up time, HF mode fOSC = 6 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
3 V 0.5 ms
fOSC = 20 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
0.3
CL,eff Integrated effective load capacitance, HF mode(1)(2) XTS = 1 1 pF
Duty cycle, HF mode XTS = 1, Measured at ACLK,
fXT1,HF2 = 20 MHz
40% 50% 60%
fFault,HF Oscillator fault frequency, HF mode(4) XTS = 1(3) 30 300 kHz
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag.
(5) To improve EMI on the XT1 oscillator the following guidelines should be observed.
  • Keep the traces between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
  • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
  • Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT1BYPASS is set, XT1 circuits are automatically powered down. The input signal must be a digital square wave with the parametrics defined in the Schmitt-Trigger Inputs section.
(7) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

5.17 Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)(5)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IDVCC.XT2 XT2 oscillator crystal current consumption fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
3 V 200 µA
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
260
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
450
fXT2,HF0 XT2 oscillator crystal frequency, mode 0 XT2DRIVEx = 0, XT2BYPASS = 0(7) 4 8 MHz
fXT2,HF1 XT2 oscillator crystal frequency, mode 1 XT2DRIVEx = 1, XT2BYPASS = 0(7) 8 16 MHz
fXT2,HF2 XT2 oscillator crystal frequency, mode 2 XT2DRIVEx = 2, XT2BYPASS = 0(7) 16 24 MHz
fXT2,HF3 XT2 oscillator crystal frequency, mode 3 XT2DRIVEx = 3, XT2BYPASS = 0(7) 24 32 MHz
fXT2,HF,SW XT2 oscillator logic-level square-wave input frequency, bypass mode XT2BYPASS = 1(6)(7) 1.5 32 MHz
OAHF Oscillation allowance for HF crystals(8) XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450 Ω
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
tSTART,HF Start-up time fOSC = 6 MHz
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
3 V 0.5 ms
fOSC = 20 MHz
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
0.3
CL,eff Integrated effective load capacitance, HF mode(1)(2) 1 pF
Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz 40% 50% 60%
fFault,HF Oscillator fault frequency(4) XT2BYPASS = 1(3) 30 300 kHz
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag.
(5) To improve EMI on the XT2 oscillator the following guidelines should be observed.
  • Keep the traces between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
  • Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
  • Use assembly materials and techniques that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT2BYPASS is set, XT2 circuits are automatically powered down. The input signal must be a digital square wave with the parametrics defined in the Schmitt-Trigger Inputs section.
(7) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz
dfVLO/dT VLO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

5.19 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IREFO REFO oscillator current consumption TA = 25°C 1.8 V to 3.6 V 3 µA
fREFO REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
REFO absolute tolerance calibrated Full temperature range 1.8 V to 3.6 V ±3.5%
TA = 25°C 3 V ±1.5%
dfREFO/dT REFO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.01 %/°C
dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 1.0 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
tSTART REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

5.20 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fDCO(0,0) DCO frequency (0, 0)(1) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
fDCO(0,31) DCO frequency (0, 31)(1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
fDCO(1,0) DCO frequency (1, 0)(1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz
fDCO(1,31) DCO frequency (1, 31)(1) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz
fDCO(2,0) DCO frequency (2, 0)(1) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz
fDCO(2,31) DCO frequency (2, 31)(1) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz
fDCO(3,0) DCO frequency (3, 0)(1) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz
fDCO(3,31) DCO frequency (3, 31)(1) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz
fDCO(4,0) DCO frequency (4, 0)(1) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz
fDCO(4,31) DCO frequency (4, 31)(1) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz
fDCO(5,0) DCO frequency (5, 0)(1) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz
fDCO(5,31) DCO frequency (5, 31)(1) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz
fDCO(6,0) DCO frequency (6, 0)(1) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz
fDCO(6,31) DCO frequency (6, 31)(1) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz
fDCO(7,0) DCO frequency (7, 0)(1) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz
fDCO(7,31) DCO frequency (7, 31)(1) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
SDCORSEL Frequency step between range DCORSEL and DCORSEL + 1 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio
SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio
Duty cycle Measured at SMCLK 40% 50% 60%
dfDCO/dT DCO frequency temperature drift(2) fDCO = 1 MHz 0.1 %/°C
dfDCO/dVCC DCO frequency voltage drift(3) fDCO = 1 MHz 1.9 %/V
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum or maximum tap setting.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
MSP430BT5190 slas703-dco.gifFigure 5-10 Typical DCO Frequency

5.21 PMM, Brown-Out Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(DVCC_BOR_IT–) BORH on voltage,
DVCC falling level
| dDVCC/dt | < 3 V/s 1.45 V
V(DVCC_BOR_IT+) BORH off voltage,
DVCC rising level
| dDVCC/dt | < 3 V/s 0.80 1.30 1.50 V
V(DVCC_BOR_hys) BORH hysteresis 60 250 mV
tRESET Pulse duration required at RST/NMI pin to accept a reset 2 µs

5.22 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.90 V
VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.80 V
VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.60 V
VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.40 V
VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.94 V
VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V 1.84 V
VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2.0 V ≤ DVCC ≤ 3.6 V 1.64 V
VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V 1.44 V

5.23 PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVSH) SVS current consumption SVSHE = 0, DVCC = 3.6 V 0 nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 µA
V(SVSH_IT–) SVSH on voltage level(1) SVSHE = 1, SVSHRVL = 0 1.57 1.68 1.78 V
SVSHE = 1, SVSHRVL = 1 1.79 1.88 1.98
SVSHE = 1, SVSHRVL = 2 1.98 2.08 2.21
SVSHE = 1, SVSHRVL = 3 2.10 2.18 2.31
V(SVSH_IT+) SVSH off voltage level(1) SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.85 V
SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.07
SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.28
SVSHE = 1, SVSMHRRL = 3 2.20 2.30 2.42
SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.55
SVSHE = 1, SVSMHRRL = 5 2.52 2.70 2.88
SVSHE = 1, SVSMHRRL = 6 2.90 3.10 3.23
SVSHE = 1, SVSMHRRL = 7 2.90 3.10 3.23
tpd(SVSH) SVSH propagation delay SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5 µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
20
t(SVSH) SVSH on or off delay time SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
12.5 µs
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
100
dVDVCC/dt DVCC rise time 0 1000 V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.

5.24 PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVMH) SVMH current consumption SVMHE = 0, DVCC = 3.6 V 0 nA
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0 200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.5 µA
V(SVMH) SVMH on or off voltage level(1) SVMHE = 1, SVSMHRRL = 0 1.62 1.74 1.85 V
SVMHE = 1, SVSMHRRL = 1 1.88 1.94 2.07
SVMHE = 1, SVSMHRRL = 2 2.07 2.14 2.28
SVMHE = 1, SVSMHRRL = 3 2.20 2.30 2.42
SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.55
SVMHE = 1, SVSMHRRL = 5 2.52 2.70 2.88
SVMHE = 1, SVSMHRRL = 6 2.90 3.10 3.23
SVMHE = 1, SVSMHRRL = 7 2.90 3.10 3.23
SVMHE = 1, SVMHOVPE = 1 3.75
tpd(SVMH) SVMH propagation delay SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5 µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
20
t(SVMH) SVMH on or off delay time SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
12.5 µs
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
100
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.

5.25 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVSL) SVSL current consumption SVSLE = 0, PMMCOREV = 2 0 nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 µA
tpd(SVSL) SVSL propagation delay SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5 µs
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
20
t(SVSL) SVSL on or off delay time SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
12.5 µs
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
100

5.26 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVML) SVML current consumption SVMLE = 0, PMMCOREV = 2 0 nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0 200
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA
tpd(SVML) SVML propagation delay SVMLE = 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
2.5 µs
SVMLE = 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
20
t(SVML) SVML on or off delay time SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
12.5 µs
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
100

5.27 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode(1) PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
fMCLK ≥ 4.0 MHz 5 µs
fMCLK < 4.0 MHz 6
tWAKE-UP-SLOW Wake-up time from LPM2, LPM3 or LPM4 to active mode(2) PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
150 165 µs
tWAKE-UP-LPM5 Wake-up time from LPM4.5 to active mode(3) 2 3 ms
tWAKE-UP-RESET Wake-up time from RST or BOR event to active mode(3) 2 3 ms
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wakeup times are possible with SVSL and SVML in full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSL and SVML are in normal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(3) This value represents the time from the wake-up event to the reset vector execution.

5.28 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fTA Timer_A input clock frequency Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
1.8 V, 3 V 25 MHz
tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V 20 ns

5.29 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fTB Timer_B input clock frequency Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%
1.8 V, 3 V 25 MHz
tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V 20 ns

5.30 USCI (UART Mode), Recommended Operating Conditions

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
fSYSTEM MHz
fBITCLK BITCLK clock frequency
(equals baud rate in MBaud)
1 MHz

5.31 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tτ UART receive deglitch time(1) 2.2 V 50 600 ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.32 USCI (SPI Master Mode), Recommended Operating Conditions

PARAMETER CONDITIONS VCC MIN MAX UNIT
fUSCI USCI input clock frequency Internal: SMCLK, ACLK
Duty cycle = 50% ±10%
fSYSTEM MHz

5.33 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 5-11 and Figure 5-12)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fUSCI USCI input clock frequency SMCLK, ACLK
Duty cycle = 50% ±10%
fSYSTEM MHz
tSU,MI SOMI input data setup time PMMCOREV = 0 1.8 V 55 ns
3 V 38
PMMCOREV = 3 2.4 V 30
3 V 25
tHD,MI SOMI input data hold time PMMCOREV = 0 1.8 V 0 ns
3 V 0
PMMCOREV = 3 2.4 V 0
3 V 0
tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
1.8 V 20 ns
3 V 18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
2.4 V 16
3 V 15
tHD,MO SIMO output data hold time(3) CL = 20 pF, PMMCOREV = 0 1.8 V –10 ns
3 V –8
CL = 20 pF, PMMCOREV = 3 2.4 V –10
3 V –8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11 and Figure 5-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-11 and Figure 5-12.
MSP430BT5190 slas703-spi_mst_ckph0.gifFigure 5-11 SPI Master Mode, CKPH = 0
MSP430BT5190 slas703-spi_mst_ckph1.gifFigure 5-12 SPI Master Mode, CKPH = 1

5.34 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 5-13 and Figure 5-14)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
tSTE,LEAD STE lead time, STE low to clock PMMCOREV = 0 1.8 V 11 ns
3 V 8
PMMCOREV = 3 2.4 V 7
3 V 6
tSTE,LAG STE lag time, Last clock to STE high PMMCOREV = 0 1.8 V 3 ns
3 V 3
PMMCOREV = 3 2.4 V 3
3 V 3
tSTE,ACC STE access time, STE low to SOMI data out PMMCOREV = 0 1.8 V 66 ns
3 V 50
PMMCOREV = 3 2.4 V 36
3 V 30
tSTE,DIS STE disable time, STE high to SOMI high impedance PMMCOREV = 0 1.8 V 30 ns
3 V 23
PMMCOREV = 3 2.4 V 16
3 V 13
tSU,SI SIMO input data setup time PMMCOREV = 0 1.8 V 5 ns
3 V 5
PMMCOREV = 3 2.4 V 2
3 V 2
tHD,SI SIMO input data hold time PMMCOREV = 0 1.8 V 5 ns
3 V 5
PMMCOREV = 3 2.4 V 5
3 V 5
tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 0
1.8 V 76 ns
3 V 60
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 3
2.4 V 44
3 V 40
tHD,SO SOMI output data hold time(3) CL = 20 pF,
PMMCOREV = 0
1.8 V 18 ns
3 V 12
CL = 20 pF,
PMMCOREV = 3
2.4 V 10
3 V 8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master), refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.
MSP430BT5190 slas703-spi_slv_ckph0.gifFigure 5-13 SPI Slave Mode, CKPH = 0
MSP430BT5190 slas703-spi_slv_ckph1.gifFigure 5-14 SPI Slave Mode, CKPH = 1

5.35 USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fUSCI USCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
fSYSTEM MHz
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
tHD,STA Hold time (repeated) START fSCL ≤ 100 kHz 2.2 V, 3 V 4.0 µs
fSCL > 100 kHz 0.6
tSU,STA Setup time for a repeated START fSCL ≤ 100 kHz 2.2 V, 3 V 4.7 µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V, 3 V 0 ns
tSU,DAT Data setup time 2.2 V, 3 V 250 ns
tSU,STO Setup time for STOP fSCL ≤ 100 kHz 2.2 V, 3 V 4.0 µs
fSCL > 100 kHz 0.6
tSP Pulse duration of spikes suppressed by input filter 2.2 V 50 600 ns
3 V 50 600
MSP430BT5190 slas703-017.gifFigure 5-15 I2C Mode Timing

5.36 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage,
full performance
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
2.2 3.6 V
V(Ax) Analog input voltage range(2) All ADC12 analog input pins Ax 0 AVCC V
IADC12_A Operating supply current into AVCC terminal(3) fADC12CLK = 5.0 MHz, ADC12ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0
2.2 V 125 155 µA
3 V 150 220
CI Input capacitance Only one terminal Ax can be selected at one time 2.2 V 20 25 pF
RI Input MUX ON resistance 0 V ≤ VAx ≤ AVCC 10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling capacitors are required. See Section 5.40 and Section 5.41.
(3) The internal reference supply current is not included in current consumption parameter IADC12_A.

5.37 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fADC12CLK For specified performance of ADC12 linearity parameters 2.2 V, 3 V 0.45 4.8 5.4 MHz
fADC12OSC Internal ADC12 oscillator(3) ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz
tCONVERT Conversion time REFON = 0, Internal oscillator,
fADC12OSC = 4.2 MHz to 5.4 MHz
2.2 V, 3 V 2.4 3.1 µs
External fADC12CLK from ACLK, MCLK or SMCLK, ADC12SSEL ≠ 0  (2)
tSample Sampling time RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
τ = [RS + RI] × CI(1)
2.2 V, 3 V 1000 ns
(1) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
(2) 13 × ADC12DIV × 1/fADC12CLK
(3) The ADC12OSC is sourced directly from MODOSC inside the UCS.

5.38 12-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EI Integral linearity error (INL) 1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V 2.2 V, 3 V ±2 LSB
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC ±1.7
ED Differential linearity error (DNL) (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V ±1.0 LSB
EO Offset error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF
2.2 V, 3 V ±1.0 ±2.0 LSB
EG Gain error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V ±1.0 ±2.0 LSB
ET Total unadjusted error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V ±1.4 ±3.5 LSB

5.39 12-Bit ADC, Temperature Sensor and Built-In VMID(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VSENSOR See (2) ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V 680 mV
3 V 680
TCSENSOR ADC12ON = 1, INCH = 0Ah 2.2 V 2.25 mV/°C
3 V 2.25
tSENSOR(sample) Sample time required if channel 10 is selected(3) ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V 100 µs
3 V 100
VMID AVCC divider at channel 11,
VAVCC factor
ADC12ON = 1, INCH = 0Bh 0.48 0.5 0.52 VAVCC
AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh 2.2 V 1.06 1.1 1.14 V
3 V 1.44 1.5 1.56
tVMID(sample) Sample time required if channel 11 is selected(4) ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V, 3 V 1000 ns
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of the temperature sensor.
(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
MSP430BT5190 vtemp_vs_temp.gifFigure 5-16 Typical Temperature Sensor Voltage

5.40 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF–(2) 1.4 AVCC V
VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF–(3) 0 1.2 V
(VeREF+ –
VREF–/VeREF–)
Differential external reference voltage input VeREF+ > VREF–/VeREF–(4) 1.4 AVCC V
IVeREF+,
IVREF–/VeREF–
Static input current 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz,ADC12SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V ±8.5 ±26 µA
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz,ADC12SHTx = 8h,
Conversion rate 20 ksps
2.2 V, 3 V ±1
CVREF+/- Capacitance at VREF+ or VREF- terminal See (5) 10 µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

5.41 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF+ Positive built-in reference voltage output REFVSEL = \{2\} for 2.5 V,
REFON = REFOUT = 1, IVREF+= 0 A
3 V 2.50 ±1.5% V
REFVSEL = \{1\} for 2.0 V,
REFON = REFOUT = 1, IVREF+= 0 A
3 V 1.98 ±1.5%
REFVSEL = \{0\} for 1.5 V,
REFON = REFOUT = 1, IVREF+= 0 A
2.2 V, 3 V 1.49 ±1.5%
AVCC(min) AVCC minimum voltage, Positive built-in reference active REFVSEL = \{0\} for 1.5 V, reduced performance 1.8 V
REFVSEL = \{0\} for 1.5 V 2.2
REFVSEL = \{1\} for 2.0 V 2.3
REFVSEL = \{2\} for 2.5 V 2.8
IREF+ Operating supply current into AVCC terminal(2)(3) REFON = 1, REFOUT = 0, REFBURST = 0 3 V 100 140 µA
REFON = 1, REFOUT = 1, REFBURST = 0 3 V 0.9 1.5 mA
IL(VREF+) Load-current regulation, VREF+ terminal(4) REFVSEL = \{0, 1, 2\},
IVREF+ = +10 µA/–1000 µA,
AVCC = AVCC(min) for each reference level,
REFVSEL = (0, 1, 2\}, REFON = REFOUT = 1
2500 µV/mA
CVREF+/- Capacitance at VREF+ and VREF- terminals REFON = REFOUT = 1(6) 20 100 pF
TCREF+ Temperature coefficient of built-in reference(5) IVREF+ = 0 A,
REFVSEL = (0, 1, 2\}, REFON = 1,
REFOUT = 0 or 1
30 50 ppm/°C
PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC(min) - AVCC(max),
TA = 25°C,
REFVSEL = (0, 1, 2\}, REFON = 1,
REFOUT = 0 or 1
120 300 µV/V
PSRR_AC Power supply rejection ratio (AC) AVCC = AVCC(min) - AVCC(max),
TA = 25°C,
f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = (0, 1, 2\}, REFON = 1,
REFOUT = 0 or 1
6.4 mV/V
tSETTLE Settling time of reference voltage(7) AVCC = AVCC(min) - AVCC(max),
REFVSEL = (0, 1, 2\}, REFOUT = 0,
REFON = 0 → 1
75 µs
AVCC = AVCC(min) - AVCC(max),
CVREF = CVREF(max),
REFVSEL = (0, 1, 2\}, REFOUT = 1,
REFON = 0 → 1
75
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference for the conversion and utilizes the smaller buffer.
(2) The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied from terminal AVCC and is equivalent to IREF+ with REFON =1 and REFOUT = 0.
(4) Contribution only due to the reference and buffer including package. This does not include resistance due to other factors such as PCB traces.
(5) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(6) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(7) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load when REFOUT = 1.

5.42 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V
IPGM Average supply current from DVCC during program 3 5 mA
IERASE Average supply current from DVCC during erase 6 11 mA
IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase 6 11 mA
tCPT Cumulative program time See (1) 16 ms
Program and erase endurance 104 105 cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time See (2) 64 85 µs
tBlock, 0 Block program time for first byte or word See (2) 49 65 µs
tBlock, 1–(N–1) Block program time for each additional byte or word, except for last byte or word See (2) 37 49 µs
tBlock, N Block program time for last byte or word See (2) 55 73 µs
tErase Erase time for segment, mass erase, and bank erase when available See (2) 23 32 ms
fMCLK,MRG MCLK frequency in marginal read mode
(FCTL4.MRG0 = 1 or FCTL4. MRG1 = 1)
0 1 MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word or byte write and block write modes.
(2) These values are hardwired into the state machine of the flash controller.

5.43 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs
tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1) 2.2 V, 3 V 1 µs
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
fTCK TCK input frequency, 4-wire JTAG(2) 2.2 V 0 5 MHz
3 V 0 10 MHz
Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.