SLAS272H July   2000  – May 2018 MSP430F133 , MSP430F135 , MSP430F147 , MSP430F1471 , MSP430F148 , MSP430F1481 , MSP430F149 , MSP430F1491

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions for MSP430F13x and MSP430F14x
      2. Table 4-2 Signal Descriptions for MSP430F14x1
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC and DVCC Excluding External Current
    5. 5.5  Thermal Resistance Characteristics
    6. 5.6  Schmitt-Trigger Inputs – Ports P1, P2, P3, P4, P5, and P6
    7. 5.7  Standard Inputs – RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    8. 5.8  Inputs – Px.y, TAx, TBx
    9. 5.9  Leakage Current
    10. 5.10 Outputs – Ports P1, P2, P3, P4, P5, and P6
    11. 5.11 Output Frequency
    12. 5.12 Typical Characteristics – Ports P1, P2, P3, P4, P5, and P6 Outputs
    13. 5.13 Wake-up Time From LPM3
    14. 5.14 RAM
    15. 5.15 Comparator_A
    16. 5.16 Typical Characteristics – Comparator_A
    17. 5.17 PUC and POR
    18. 5.18 DCO Frequency
    19. 5.19 DCO When Using ROSC
    20. 5.20 Crystal Oscillator, LFXT1
    21. 5.21 Crystal Oscillator, XT2
    22. 5.22 USART0, USART1
    23. 5.23 12-Bit ADC, Power Supply and Input Range Conditions
    24. 5.24 12-Bit ADC, External Reference
    25. 5.25 12-Bit ADC, Built-In Reference
    26. 5.26 12-Bit ADC, Timing Parameters
    27. 5.27 12-Bit ADC, Linearity Parameters
    28. 5.28 12-Bit ADC, Temperature Sensor and Built-In VMID
    29. 5.29 Flash Memory
    30. 5.30 JTAG Interface
    31. 5.31 JTAG Fuse
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Instruction set
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Bootloader (BSL)
    6. 6.6 JTAG Fuse Check Mode
    7. 6.7 Memory
      1. 6.7.1 Flash Memory
      2. 6.7.2 Special Function Registers
        1. Table 6-6   Interrupt Enable 1 Register Field Descriptions
        2. Table 6-7   Interrupt Enable 2 Register Field Descriptions
        3. Table 6-8   Interrupt Flag 1 Register Field Descriptions
        4. Table 6-9   Interrupt Flag 2 Register Field Descriptions
        5. Table 6-10 Module Enable 1 Bit Register Field Descriptions
        6. Table 6-11 Module Enable 2 Bit Register Field Descriptions
    8. 6.8 Peripherals
      1. 6.8.1  Digital I/O
      2. 6.8.2  Oscillator and System Clock
      3. 6.8.3  Watchdog Timer (WDT)
      4. 6.8.4  Hardware Multiplier (MSP430F14x and MSP430F14x1 Only)
      5. 6.8.5  USART0
      6. 6.8.6  USART1 (MSP430F14x and MSP430F14x1 Only)
      7. 6.8.7  Comparator_A
      8. 6.8.8  ADC12 (MSP430F14x and MSP430F13x Only)
      9. 6.8.9  Timer_A3
      10. 6.8.10 Timer_B3 (MSP430F13x Only)
      11. 6.8.11 Timer_B7 (MSP430F14x and MSP430F14x1 Only)
      12. 6.8.12 Peripheral File Map
    9. 6.9 Input/Output Diagrams
      1. 6.9.1 Port P1, Input/Output With Schmitt Trigger
      2. 6.9.2 Port P2, Input/Output With Schmitt Trigger
      3. 6.9.3 Port P3, Input/Output With Schmitt Trigger
      4. 6.9.4 Port P4, Input/Output With Schmitt Trigger
      5. 6.9.5 Port P5, Input/Output With Schmitt Trigger
      6. 6.9.6 Port P6, Input/Output With Schmitt Trigger
      7. 6.9.7 Port JTAG (TMS, TCK, TDI/TCLK, TDO/TDI), Input/Output With Schmitt Trigger
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8.12 Peripheral File Map

Table 6-14 lists the peripheral register that support word access. See Table 6-15 for the regsiters with byte access.

Table 6-14 Peripherals With Word Access

MODULE REGISTER NAME ACRONYM ADDRESS
Watchdog Watchdog timer control WDTCTL 0120h
Timer_B7, Timer_B3 Timer_B interrupt vector TBIV 011Eh
Timer_B control TBCTL 0180h
Timer_B capture/compare control 0 TBCCTL0 0182h
Timer_B capture/compare control 1 TBCCTL1 0184h
Timer_B capture/compare control 2 TBCCTL2 0186h
Timer_B capture/compare control 3(1) TBCCTL3 0188h
Timer_B capture/compare control 4(1) TBCCTL4 018Ah
Timer_B capture/compare control 5(1) TBCCTL5 018Ch
Timer_B capture/compare control 6(1) TBCCTL6 018Eh
Timer_B counter TBR 0190h
Timer_B capture/compare 0 TBCCR0 0192h
Timer_B capture/compare 1 TBCCR1 0194h
Timer_B capture/compare 2 TBCCR2 0196h
Timer_B capture/compare 3(1) TBCCR3 0198h
Timer_B capture/compare 4(1) TBCCR4 019Ah
Timer_B capture/compare 5(1) TBCCR5 019Ch
Timer_B capture/compare 6(1) TBCCR6 019Eh
Timer_A3 Timer_A interrupt vector TAIV 012Eh
Timer_A control TACTL 0160h
Timer_A capture/compare control 0 TACCTL0 0162h
Timer_A capture/compare control 1 TACCTL1 0164h
Timer_A capture/compare control 2 TACCTL2 0166h
Reserved 0168h
Reserved 016Ah
Reserved 016Ch
Reserved 016Eh
Timer_A counter TAR 0170h
Timer_A capture/compare 0 TACCR0 0172h
Timer_A capture/compare 1 TACCR1 0174h
Timer_A capture/compare 2 TACCR2 0176h
Reserved 0178h
Reserved 017Ah
Reserved 017Ch
Reserved 017Eh
Hardware multiplier (MSP430F14x and MSP430F14x1 only) Sum extend SUMEXT 013Eh
Result high word RESHI 013Ch
Result low word RESLO 013Ah
Operand 2 OP2 0138h
Multiply signed and accumulate operand 1 MACS 0136h
Multiply and accumulate operand 1 MAC 0134h
Multiply signed operand 1 MPYS 0132h
Multiply unsigned operand 1 MPY 0130h
Flash Flash control 3 FCTL1 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
ADC12 (not in MSP430F14x1) Conversion memory 15 ADC12MEM15 015Eh
Conversion memory 14 ADC12MEM14 015Ch
Conversion memory 13 ADC12MEM13 015Ah
Conversion memory 12 ADC12MEM12 0158h
Conversion memory 11 ADC12MEM11 0156h
Conversion memory 10 ADC12MEM10 0154h
Conversion memory 9 ADC12MEM9 0152h
Conversion memory 8 ADC12MEM8 0150h
Conversion memory 7 ADC12MEM7 014Eh
Conversion memory 6 ADC12MEM6 014Ch
Conversion memory 5 ADC12MEM5 014Ah
Conversion memory 4 ADC12MEM4 0148h
Conversion memory 3 ADC12MEM3 0146h
Conversion memory 2 ADC12MEM2 0144h
Conversion memory 1 ADC12MEM1 0142h
Conversion memory 0 ADC12MEM0 0140h
Interrupt vector word ADC12IV 01A8h
Interrupt enable ADC12IE 01A6h
Interrupt flag ADC12IFG 01A4h
ADC control 1 ADC12CTL1 01A2h
ADC control 0 ADC12CTL0 01A0h
ADC memory control 15 ADC12MCTL15 08Fh
ADC memory control 14 ADC12MCTL14 08Eh
ADC memory control 13 ADC12MCTL13 08Dh
ADC memory control 12 ADC12MCTL12 08Ch
ADC memory control 11 ADC12MCTL11 08Bh
ADC memory control 10 ADC12MCTL10 08Ah
ADC memory control 9 ADC12MCTL9 089h
ADC memory control 8 ADC12MCTL8 088h
ADC memory control 7 ADC12MCTL7 087h
ADC memory control 6 ADC12MCTL6 086h
ADC memory control 5 ADC12MCTL5 085h
ADC memory control 4 ADC12MCTL4 084h
ADC memory control 3 ADC12MCTL3 083h
ADC memory control 2 ADC12MCTL2 082h
ADC memory control 1 ADC12MCTL1 081h
ADC memory control 0 ADC12MCTL0 080h
(1) Timer_B7 only, reserved for Timer_B3

Table 6-15 lists the peripheral register that support byte access. See Table 6-14 for the regsiters with word access.

Table 6-15 Peripherals With Byte Access

MODULE REGISTER NAME ACRONYM ADDRESS
USART1 (MSP430F14x and MSP430F14x1 only) Transmit buffer U1TXBUF 07Fh
Receive buffer U1RXBUF 07Eh
Baud rate 1 U1BR1 07Dh
Baud rate 0 U1BR0 07Ch
Modulation control U1MCTL 07Bh
Receive control U1RCTL 07Ah
Transmit control U1TCTL 079h
USART control U1CTL 078h
USART0 Transmit buffer U0TXBUF 077h
Receive buffer U0RXBUF 076h
Baud rate 1 U0BR1 075h
Baud rate 0 U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Comparator_A Comparator_A port disable CAPD 05Bh
Comparator_A control 2 CACTL2 05Ah
Comparator_A control 1 CACTL1 059h
Basic Clock Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P6 Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Functions SFR module enable 2 ME2 005h
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h