SLAS541L June   2007  – May 2020 MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Current (Into VCC)
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics – LPM4 Current
    8. 5.8  Schmitt-Trigger Inputs (Ports P1 to P8, RST/NMI, JTAG, XIN, and XT2IN)
    9. 5.9  Inputs (Ports P1 and P2)
    10. 5.10 Leakage Current (Ports P1 to P8)
    11. 5.11 Standard Inputs (RST/NMI)
    12. 5.12 Outputs (Ports P1 to P8)
    13. 5.13 Output Frequency (Ports P1 to P8)
    14. 5.14 Typical Characteristics – Outputs
    15. 5.15 POR and Brownout Reset (BOR)
    16. 5.16 Typical Characteristics – POR and BOR
    17. 5.17 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
    18. 5.18 Main DCO Characteristics
    19. 5.19 DCO Frequency
    20. 5.20 Calibrated DCO Frequencies – Tolerance at Calibration
    21. 5.21 Calibrated DCO Frequencies – Tolerance Over Temperature 0°C to 85°C
    22. 5.22 Calibrated DCO Frequencies – Tolerance Over Supply Voltage VCC
    23. 5.23 Calibrated DCO Frequencies – Overall Tolerance
    24. 5.24 Typical Characteristics – Calibrated DCO Frequency
    25. 5.25 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    26. 5.26 Typical Characteristics – DCO Clock Wake-up Time From LPM3 or LPM4
    27. 5.27 DCO With External Resistor ROSC
    28. 5.28 Typical Characteristics – DCO With External Resistor ROSC
    29. 5.29 Crystal Oscillator LFXT1, Low-Frequency Mode
    30. 5.30 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    31. 5.31 Crystal Oscillator LFXT1, High-Frequency Mode
    32. 5.32 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)
    33. 5.33 Crystal Oscillator XT2
    34. 5.34 Typical Characteristics – XT2 Oscillator
    35. 5.35 Timer_A
    36. 5.36 Timer_B
    37. 5.37 USCI (UART Mode)
    38. 5.38 USCI (SPI Master Mode)
    39. 5.39 USCI (SPI Slave Mode)
    40. 5.40 USCI (I2C Mode)
    41. 5.41 Comparator_A+
    42. 5.42 Typical Characteristics, Comparator_A+
    43. 5.43 12-Bit ADC Power Supply and Input Range Conditions
    44. 5.44 12-Bit ADC External Reference
    45. 5.45 12-Bit ADC Built-In Reference
    46. 5.46 12-Bit ADC Timing Parameters
    47. 5.47 12-Bit ADC Linearity Parameters
    48. 5.48 12-Bit ADC Temperature Sensor and Built-In VMID
    49. 5.49 12-Bit DAC Supply Specifications
    50. 5.50 12-Bit DAC Linearity Specifications
    51. 5.51 Typical Characteristics, 12-Bit DAC Linearity Specifications
    52. 5.52 12-Bit DAC Output Specifications
    53. 5.53 12-Bit DAC Reference Input Specifications
    54. 5.54 12-Bit DAC Dynamic Specifications
    55. 5.55 Flash Memory
    56. 5.56 RAM
    57. 5.57 JTAG Interface
    58. 5.58 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. Table 6-4 Interrupt Enable Register 1 Description
      2. Table 6-5 Interrupt Enable Register 2 Description
      3. Table 6-6 Interrupt Flag Register 1 Description
      4. Table 6-7 Interrupt Flag Register 2 Description
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller (MSP430F261x Only)
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Calibration Data Stored in Information Memory Segment A
      4. 6.9.4  Brownout, Supply Voltage Supervisor (SVS)
      5. 6.9.5  Digital I/O
      6. 6.9.6  Watchdog Timer (WDT+)
      7. 6.9.7  Hardware Multiplier
      8. 6.9.8  Universal Serial Communication Interface (USCI)
      9. 6.9.9  Timer_A3
      10. 6.9.10 Timer_B7
      11. 6.9.11 Comparator_A+
      12. 6.9.12 ADC12
      13. 6.9.13 DAC12 (MSP430F261x Only)
      14. 6.9.14 Peripheral File Map
    10. 6.10 Port Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7), Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.0 to P2.4, P2.6, and P2.7), Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.5), Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 to P3.7), Input/Output With Schmitt Trigger
      5. 6.10.5  Port P4 (P4.0 to P4.7), Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger
      7. 6.10.7  Port P6 (P6.0 to P6.4), Input/Output With Schmitt Trigger
      8. 6.10.8  Port P6 (P6.5 and P6.6), Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6 (P6.7), Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger
      11. 6.10.11 Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger
      12. 6.10.12 Port P8 (P8.6), Input/Output With Schmitt Trigger
      13. 6.10.13 Port P8 (P8.7), Input/Output With Schmitt Trigger
      14. 6.10.14 JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI) Input/Output With Schmitt Trigger
      15. 6.10.15 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1  Getting Started
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Signal Descriptions

TERMINAL I/O DESCRIPTION
NAME NO.
PM 64‑PIN PN 80‑PIN ZCA or ZQW 113‑PIN
AVCC 64 80 A2 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
AVSS 62 78 B2, B3 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
DVCC1 1 1 A1 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1 63 79 A3 Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2 52 F12 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2 53 E12 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK/CAOUT 12 12 G2 I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
Comparator_A output
P1.1/TA0 13 13 H1 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
BSL transmit
P1.2/TA1 14 14 H2 I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 15 15 J1 I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 16 J2 I/O General-purpose digital I/O pin
SMCLK signal output
P1.5/TA0 17 17 K1 I/O General-purpose digital I/O pin
Timer_A, compare: Out0 output
P1.6/TA1 18 18 K2 I/O General-purpose digital I/O pin
Timer_A, compare: Out1 output
P1.7/TA2 19 19 L1 I/O General-purpose digital I/O pin
Timer_A, compare: Out2 output
P2.0/ACLK/CA2 20 20 M1 I/O General-purpose digital I/O pin
ACLK output
Comparator_A input
P2.1/TAINCLK/CA3 21 21 M2 I/O General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0/CA4 22 22 M3 I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input
Comparator_A output
BSL receive
Comparator_A input
P2.3/CA0/TA1 23 23 L3 I/O General-purpose digital I/O pin
Timer_A, compare: Out1 output
Comparator_A input
P2.4/CA1/TA2 24 24 L4 I/O General-purpose digital I/O pin
Timer_A, compare: Out2 output
Comparator_A input
P2.5/ROSC/CA5 25 25 M4 I/O General-purpose digital I/O pin
Input for external resistor defining the DCO nominal frequency
Comparator_A input
P2.6/ADC12CLK/ DMAE0(1)/CA6 26 26 J4 I/O General-purpose digital I/O pin
Conversion clock for 12-bit ADC
DMA channel 0 external trigger
Comparator_A input
P2.7/TA0/CA7 27 27 L5 I/O General-purpose digital I/O pin
Timer_A, compare: Out0 output
Comparator_A input
P3.0/UCB0STE/ UCA0CLK 28 28 M5 I/O General-purpose digital I/O pin
USCI_B0 slave transmit enable
USCI_A0 clock input/output
P3.1/UCB0SIMO/ UCB0SDA 29 29 L6 I/O General-purpose digital I/O pin
USCI_B0 slave in master out for SPI mode
USCI_B0 SDA I2C data in I2C mode
P3.2/UCB0SOMI/ UCB0SCL 30 30 M6 I/O General-purpose digital I/O pin
USCI_B0 slave out master in for SPI mode
USCI_B0 SCL I2C clock in I2C mode
P3.3/UCB0CLK/ UCA0STE 31 31 L7 I/O General-purpose digital I/O
USCI_B0 clock input/output
USCI_A0 slave transmit enable
P3.4/UCA0TXD/ UCA0SIMO 32 32 M7 I/O General-purpose digital I/O pin
USCI_A transmit data output in UART mode
USCI_A slave data in/master out for SPI mode
P3.5/UCA0RXD/ UCA0SOMI 33 33 L8 I/O General-purpose digital I/O pin
USCI_A0 receive data input in UART mode
USCI_A0 slave data out/master in for SPI mode
P3.6/UCA1TXD/ UCA1SIMO 34 34 M8 I/O General-purpose digital I/O pin
USCI_A1 transmit data output in UART mode
USCI_A1 slave data in/master out for SPI mode
P3.7/UCA1RXD/ UCA1SOMI 35 35 L9 I/O General-purpose digital I/O pin
USCI_A1 receive data input in UART mode
USCI_A1 slave data out/master in for SPI mode
P4.0/TB0 36 36 M9 I/O General-purpose digital I/O pin
Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1 37 37 J9 I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2 38 38 M10 I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3 39 39 L10 I/O General-purpose digital I/O pin
Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4 40 40 M11 I/O General-purpose digital I/O pin
Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5 41 41 M12 I/O General-purpose digital I/O pin
Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6 42 42 L12 I/O General-purpose digital I/O pin
Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK 43 43 K11 I/O General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
P5.0/UCB1STE/ UCA1CLK 44 44 K12 I/O General-purpose digital I/O pin
USCI_B1 slave transmit enable
USCI_A1 clock input/output
P5.1/UCB1SIMO/ UCB1SDA 45 45 J11 I/O General-purpose digital I/O pin
USCI_B1 slave in master out for SPI mode
USCI_B1 SDA I2C data in I2C mode
P5.2/UCB1SOMI/ UCB1SCL 46 46 J12 I/O General-purpose digital I/O pin
USCI_B1 slave out master in for SPI mode
USCI_B1 SCL I2C clock in I2C mode
P5.3/UCB1CLK/ UCA1STE 47 47 H11 I/O General-purpose digital I/O
USCI_B1 clock input/output
USCI_A1 slave transmit enable
P5.4/MCLK 48 48 H12 I/O General-purpose digital I/O pin
Main system clock MCLK output
P5.5/SMCLK 49 49 G11 I/O General-purpose digital I/O pin
Submain system clock SMCLK output
P5.6/ACLK 50 50 G12 I/O General-purpose digital I/O pin
Auxiliary clock ACLK output
P5.7/TBOUTH/SVSOUT 51 51 F11 I/O General-purpose digital I/O pin
Switch all PWM digital output ports to high impedance – Timer_B TB0 to TB6
SVS comparator output
P6.0/A0 59 75 D4 I/O General-purpose digital I/O pin
Analog input A0 for 12-bit ADC
P6.1/A1 60 76 A4 I/O General-purpose digital I/O pin
Analog input A1 for 12-bit ADC
P6.2/A2 61 77 B4 I/O General-purpose digital I/O pin
Analog input A2 for 12-bit ADC
P6.3/A3 2 2 B1 I/O General-purpose digital I/O pin
Analog input A3 for 12-bit ADC
P6.4/A4 3 3 C1 I/O General-purpose digital I/O pin
Analog input A4 for 12-bit ADC
P6.5/A5/DAC1(1) 4 4 C2,
C3
I/O General-purpose digital I/O pin
Analog input A5 for 12-bit ADC
DAC12.1 output
P6.6/A6/DAC0(1) 5 5 D1 I/O General-purpose digital I/O pin
Analog input A6 for 12-bit ADC
DAC12.0 output
P6.7/A7/DAC1(1)/SVSIN 6 6 D2 I/O General-purpose digital I/O pin
Analog input A7 for 12-bit ADC
DAC12.1 output
SVS input
P7.0 54 E11 I/O General-purpose digital I/O pin
P7.1 55 D12 I/O General-purpose digital I/O pin
P7.2 56 D11 I/O General-purpose digital I/O pin
P7.3 57 C12 I/O General-purpose digital I/O pin
P7.4 58 C11 I/O General-purpose digital I/O pin
P7.5 59 B12 I/O General-purpose digital I/O pin
P7.6 60 A12 I/O General-purpose digital I/O pin
P7.7 61 A11 I/O General-purpose digital I/O pin
P8.0 62 B10 I/O General-purpose digital I/O pin
P8.1 63 A10 I/O General-purpose digital I/O pin
P8.2 64 D9 I/O General-purpose digital I/O pin
P8.3 65 A9 I/O General-purpose digital I/O pin
P8.4 66 B9 I/O General-purpose digital I/O pin
P8.5 67 B8 I/O General-purpose digital I/O pin
P8.6/XT2OUT 68 A8 I/O General-purpose digital I/O pin
Output terminal of crystal oscillator XT2
P8.7/XT2IN 69 A7 I/O General-purpose digital I/O pin
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT 52 O Output terminal of crystal oscillator XT2
XT2IN 53 I Input port for crystal oscillator XT2
RST/NMI 58 74 B5 I Reset input, nonmaskable interrupt input port, or bootloader start (in flash devices)
TCK 57 73 A5 I Test clock (JTAG). TCK is the clock input port for device programming test and bootloader start
TDI/TCLK 55 71 A6 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 54 70 B7 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TMS 56 72 B6 I Test mode select. TMS is used as an input port for device programming and test.
VeREF+/DAC0(1) 10 10 F2 I Input for an external reference voltage
DAC12.0 output
VREF+ 7 7 E2 O Output of positive terminal of the reference voltage in the ADC12
VREF-/VeREF- 11 11 G1 I Negative terminal for the reference voltage for both sources, the internal reference voltage or an external applied reference voltage
XIN 8 8 E1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 9 F1 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
Reserved  (2) NA Reserved pins. TI recommends connecting to DVSS and AVSS.
MSP430F261x devices only
Reserved pins are L2, E4, F4, G4, H4, D5, E5, F5, G5, H5, J5, D6, E6, H6, J6, D7, E7, H7, J7, D8, E8, F8, G8, H8, J8, E9, F9, G9, H9, B11, L11.