SLAS612F August   2009  – September 2018 MSP430F5418 , MSP430F5419 , MSP430F5435 , MSP430F5436 , MSP430F5437 , MSP430F5438

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 5.8  Inputs – Ports P1 and P2
    9. 5.9  Leakage Current – General-Purpose I/O
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 5.12 Output Frequency – General-Purpose I/O
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2
    18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20 DCO Frequency
    21. 5.21 PMM, Brownout Reset (BOR)
    22. 5.22 PMM, Core Voltage
    23. 5.23 PMM, SVS High Side
    24. 5.24 PMM, SVM High Side
    25. 5.25 PMM, SVS Low Side
    26. 5.26 PMM, SVM Low Side
    27. 5.27 Wake-up Times From Low-Power Modes
    28. 5.28 Timer_A
    29. 5.29 Timer_B
    30. 5.30 USCI (UART Mode) Clock Frequency
    31. 5.31 USCI (UART Mode)
    32. 5.32 USCI (SPI Master Mode) Clock Frequency
    33. 5.33 USCI (SPI Master Mode)
    34. 5.34 USCI (SPI Slave Mode)
    35. 5.35 USCI (I2C Mode)
    36. 5.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 5.37 12-Bit ADC, External Reference
    38. 5.38 12-Bit ADC, Built-In Reference
    39. 5.39 12-Bit ADC, Timing Parameters
    40. 5.40 12-Bit ADC, Linearity Parameters
    41. 5.41 12-Bit ADC, Temperature Sensor and Built-In VMID
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Oscillator and System Clock (Link to User's Guide)
      3. 6.9.3  Power-Management Module (PMM) (Link to User's Guide)
      4. 6.9.4  Hardware Multiplier (Link to User's Guide)
      5. 6.9.5  Real-Time Clock (RTC_A) (Link to User's Guide)
      6. 6.9.6  Watchdog Timer (WDT_A) (Link to User's Guide)
      7. 6.9.7  System Module (SYS) (Link to User's Guide)
      8. 6.9.8  DMA Controller (Link to User's Guide)
      9. 6.9.9  Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      10. 6.9.10 TA0 (Link to User's Guide)
      11. 6.9.11 TA1 (Link to User's Guide)
      12. 6.9.12 TB0 (Link to User's Guide)
      13. 6.9.13 ADC12_A (Link to User's Guide)
      14. 6.9.14 CRC16 (Link to User's Guide)
      15. 6.9.15 Embedded Emulation Module (EEM) (L Version) (Link to User's Guide)
      16. 6.9.16 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
      18. 6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      19. 6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 TLV (Device Descriptor) Structures
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11 TLV (Device Descriptor) Structures

Table 6-58 lists the complete contents of the device descriptor tag-length-value (TLV) structure.

Table 6-58 Device Descriptor Table(1)

DESCRIPTION ADDRESS SIZE
(bytes)		 VALUE
F5438 F5437 F5436 F5435 F5419 F5418
Info Block Info length 01A00h 1 06h 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h 06h
CRC value 01A02h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Device ID 01A04h 1 54h 54h 54h 54h 54h 54h
Device ID 01A05h 1 38h 37h 36h 35h 19h 18h
Hardware revision 01A06h 1 Per unit Per unit Per unit Per unit Per unit Per unit
Firmware revision 01A07h 1 Per unit Per unit Per unit Per unit Per unit Per unit
Die Record Die record tag 01A08h 1 08h 08h 08h 08h 08h 08h
Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/wafer ID 01A0Ah 4 Per unit Per unit Per unit Per unit Per unit Per unit
Die X position 01A0Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit
Die Y position 01A10h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Test results 01A12h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC12 Calibration ADC12 calibration tag 01A14h 1 10h 10h 10h 10h 10h 10h
ADC12 calibration length 01A15h 1 10h 10h 10h 10h 10h 10h
ADC gain factor 01A16h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC offset 01A18h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference factor 01A1Ah 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference
Temperature sensor 30°C		 01A1Ch 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 1.5-V reference
Temperature sensor 85°C		 01A1Eh 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 2.5-V reference factor 01A20h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 2.5-V reference
Temperature sensor 30°C		 01A22h 2 Per unit Per unit Per unit Per unit Per unit Per unit
ADC 2.5-V reference
Temperature sensor 85°C		 01A24h 2 Per unit Per unit Per unit Per unit Per unit Per unit
Peripheral Descriptor Peripheral descriptor tag 01A26h 1 02h 02h 02h 02h 02h 02h
Peripheral descriptor length 01A27h 1 5Dh 55h 5Eh 56h 5Dh 55h
Memory 1 2 08h
8Ah		 08h
8Ah		 08h
8Ah		 08h
8Ah		 08h
8Ah		 08h
8Ah
Memory 2 2 0Ch
86h		 0Ch
86h		 0Ch
86h		 0Ch
86h		 0Ch
86h		 0Ch
86h
Memory 3 2 0Eh
30h		 0Eh
30h		 0Eh
30h		 0Eh
30h		 0Eh
30h		 0Eh
30h
Memory 4 2 2Eh
98h		 2Eh
98h		 2Eh
97h		 2Eh
97h		 2Eh
96h		 2Eh
96h
Memory 5 0/1 N/A N/A 94h 94h N/A N/A
Delimiter 1 00h 00h 00h 00h 00h 00h
Peripheral count 1 1Fh 1Bh 1Fh 1Fh 1Fh 1Bh
MSP430CPUXV2 2 00h
23h		 00h
23h		 00h
23h		 00h
23h		 00h
23h		 00h
23h
Peripheral Descriptor (continued) SBW 2 00h
0Fh		 00h
0Fh		 00h
0Fh		 00h
0Fh		 00h
0Fh		 00h
0Fh
EEM-8 2 00h
05h		 00h
05h		 00h
05h		 00h
05h		 00h
05h		 00h
05h
TI BSL 2 00h
FCh		 00h
FCh		 00h
FCh		 00h
FCh		 00h
FCh		 00h
FCh
Package 2 00h
1Fh		 00h
1Fh		 00h
1Fh		 00h
1Fh		 00h
1Fh		 00h
1Fh
SFR 2 10h
41h		 10h
41h		 10h
41h		 10h
41h		 10h
41h		 10h
41h
PMM 2 02h
30h		 02h
30h		 02h
30h		 02h
30h		 02h
30h		 02h
30h
FCTL 2 02h
38h		 02h
38h		 02h
38h		 02h
38h		 02h
38h		 02h
38h
CRC16 2 01h
3Dh		 01h
3Dh		 01h
3Dh		 01h
3Dh		 01h
3Dh		 01h
3Dh
RAMCTL 2 00h
44h		 00h
44h		 00h
44h		 00h
44h		 00h
44h		 00h
44h
WDT_A 2 00h
40h		 00h
40h		 00h
40h		 00h
40h		 00h
40h		 00h
40h
UCS 2 01h
48h		 01h
48h		 01h
48h		 01h
48h		 01h
48h		 01h
48h
SYS 2 02h
42h		 02h
42h		 02h
42h		 02h
42h		 02h
42h		 02h
42h
Port 1 and 2 2 08h
51h		 08h
51h		 08h
51h		 08h
51h		 08h
51h		 08h
51h
Port 3 and 4 2 02h
52h		 02h
52h		 02h
52h		 02h
52h		 02h
52h		 02h
52h
Port 5 and 6 2 02h
53h		 02h
53h		 02h
53h		 02h
53h		 02h
53h		 02h
53h
Port 7 and 8 2 02h
54h		 02h
54h		 02h
54h		 02h
54h		 02h
54h		 02h
54h
Port 9 and 10 2 02h
55h		 N/A 02h
55h		 N/A 02h
55h		 N/A
Port 11 and 12 2 02h
56h		 N/A 02h
56h		 N/A 02h
56h		 N/A
JTAG 2 08h
5Fh		 0Ch
5F		 08h
5Fh		 0Ch
5F		 08h
5Fh		 0Ch
5F
TA0 2 02h
62h		 02h
62h		 02h
62h		 02h
62h		 02h
62h		 02h
62h
TA1 2 04h
61h		 04h
61h		 04h
61h		 04h
61h		 04h
61h		 04h
61h
TB0 2 04h
67h		 04h
67h		 04h
67h		 04h
67h		 04h
67h		 04h
67h
RTC 2 0Eh
68h		 0Eh
68h		 0Eh
68h		 0Eh
68h		 0Eh
68h		 0Eh
68h
MPY32 2 02h
85h		 02h
85h		 02h
85h		 02h
85h		 02h
85h		 02h
85h
DMA-3 2 04h
47h		 04h
47h		 04h
47h		 04h
47h		 04h
47h		 04h
47h
USCI_A and USCI_B 2 0Ch
90h		 0Ch
90h		 0Ch
90h		 0Ch
90h		 0Ch
90h		 0Ch
90h
Peripheral Descriptor (continued) USCI_A and USCI_B 2 04h
90h		 04h
90h		 04h
90h		 04h
90h		 04h
90h		 04h
90h
USCI_A and USCI_B 2 04h
90h		 N/A 04h
90h		 N/A 04h
90h		 N/A
USCI_A and USCI_B 2 04h
90h		 N/A 04h
90h		 N/A 04h
90h		 N/A
ADC12_A 2 08h
D0h		 10h
D0h		 08h
D0h		 10h
D0h		 08h
D0h		 10h
D0h
Interrupts TB0.CCIFG0 1 64h 64h 64h 64h 64h 64h
TB0.CCIFG1..6 1 65h 65h 65h 65h 65h 65h
WDTIFG 1 40h 40h 40h 40h 40h 40h
USCI_A0 1 90h 90h 90h 90h 90h 90h
USCI_B0 1 91h 91h 91h 91h 91h 91h
ADC12_A 1 D0h D0h D0h D0h D0h D0h
TA0.CCIFG0 1 60h 60h 60h 60h 60h 60h
TA0.CCIFG1..4 1 61h 61h 61h 61h 61h 61h
USCI_A2 1 94h 01h 94h 01h 94h 01h
USCI_B2 1 95h 01h 95h 01h 95h 01h
DMA 1 46h 46h 46h 46h 46h 46h
TA1.CCIFG0 1 62h 62h 62h 62h 62h 62h
TA1.CCIFG1..2 1 63h 63h 63h 63h 63h 63h
P1 1 50h 50h 50h 50h 50h 50h
USCI_A1 1 92h 92h 92h 92h 92h 92h
USCI_B1 1 93h 93h 93h 93h 93h 93h
USCI_A3 1 96h 01h 96h 01h 96h 01h
USCI_B3 1 97h 01h 97h 01h 97h 01h
P2 1 51h 51h 51h 51h 51h 51h
RTC_A 1 68h 68h 68h 68h 68h 68h
Delimiter 1 00h 00h 00h 00h 00h 00h
(1) N/A = Not applicable