MSP430F5438 18 MHz MCU with 256KB Flash, 16KB SRAM, 12-bit ADC, DMA, UART/SPI/I2C, Timer, HW Multiplier | TI.com

MSP430F5438
NOT RECOMMENDED FOR NEW DESIGNS
This product continues to be in production to support existing customers.
18 MHz MCU with 256KB Flash, 16KB SRAM, 12-bit ADC, DMA, UART/SPI/I2C, Timer, HW Multiplier

18 MHz MCU with 256KB Flash, 16KB SRAM, 12-bit ADC, DMA, UART/SPI/I2C, Timer, HW Multiplier - MSP430F5438
Datasheet
MSP430F543x, MSP430F541x Mixed-Signal Microcontrollers datasheet (Rev. F)
Errata
 

This product is not recommended for new designs.

Replaced By MSP430F5438A – The device has the SAME FUNCTIONALITY and PINOUT as the compared device but is NOT an exact equivalent.

TI does not recommend using this part in a new design. This product continues to be in production to support existing customers.

Description

The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in less than 5 µs.

The MSP430F543x and MSP430F541x microcontrollers have three 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC), up to four universal serial communication interfaces (USCIs), a hardware multiplier, DMA, a real-time clock (RTC) module with alarm capabilities, and up to 87 I/O pins.

For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User’s Guide.

Features

  • Low Supply Voltage Range: 2.2 V to 3.6 V
  • Ultra-Low Power Consumption
    • Active Mode (AM): All System Clocks Active
      • 312 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical)
      • 140 µA/MHz at 8 MHz, 3.0 V, RAM Program Execution (Typical)
    • Standby Mode (LPM3):
      • Real-Time Clock (RTC) With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wake up: 2.6 µA at 3.0 V (Typical)
      • Low-Power Oscillator (VLO), General-Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup: 1.8 µA at 3.0 V (Typical)
    • Off Mode (LPM4):
      Full RAM Retention, Supply Supervisor Operational, Fast Wakeup:
      1.69 µA at 3.0 V (Typical)
  • Wake up From Standby Mode in Less Than 5 µs
  • 16-Bit RISC Architecture
    • Extended Memory
    • Up to 18-MHz System Clock
  • Flexible Power-Management System
    • Fully Integrated LDO With Programmable Regulated Core Supply Voltage
    • Supply Voltage Supervision, Monitoring, and Brownout
  • Unified Clock System (UCS)
    • FLL Control Loop for Frequency Stabilization
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • Low-Frequency Trimmed Internal Reference Source (REFO)
    • 32-kHz Crystals
    • High-Frequency Crystals up to 32 MHz
  • 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers
  • 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers
  • Up to Four Universal Serial Communication Interfaces
    • USCI_A0, USCI_A1, USCI_A2, and USCI_A3 Each Support:
      • Enhanced UART Supports Automatic Baud-Rate Detection
      • IrDA Encoder and Decoder
      • Synchronous SPI
    • USCI_B0, USCI_B1, USCI_B2, and USCI_B3 Each Support:
      • I2C
      • Synchronous SPI
  • 12-Bit Analog-to-Digital Converter (ADC)
    • Internal Reference
    • Sample-and-Hold
    • Autoscan Feature
    • 14 External Channels, 2 Internal Channels
  • Hardware Multiplier Supporting 32-Bit Operations
  • Serial Onboard Programming, No External Programming Voltage Needed
  • 3-Channel Internal DMA
  • Basic Timer With RTC Feature
  • Device Comparison Summarizes the Available Family Members

All trademarks are the property of their respective owners.