SLASE46A February   2015  – October 2018 MSP430F6720A , MSP430F6721A , MSP430F6723A , MSP430F6724A , MSP430F6725A , MSP430F6726A , MSP430F6730A , MSP430F6731A , MSP430F6733A , MSP430F6734A , MSP430F6735A , MSP430F6736A


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-5 Signal Descriptions, PZ Package
      2. Table 4-6 Signal Descriptions, PN Package
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1  Power Supply Sequencing
      2. 5.8.2  Reset Timing
        1. Table 5-1 Wake-up Times From Low-Power Modes and Reset
      3. 5.8.3  Clock Specifications
        1. Table 5-2 Crystal Oscillator, XT1, Low-Frequency Mode
        2. Table 5-3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        3. Table 5-4 Internal Reference, Low-Frequency Oscillator (REFO)
        4. Table 5-5 DCO Frequency
      4. 5.8.4  Digital I/O Ports
        1. Table 5-6  Schmitt-Trigger Inputs, General-Purpose I/O
        2. Table 5-7  Inputs, Ports P1 and P2
        3. Table 5-8  Leakage Current, General-Purpose I/O
        4. Table 5-9  Outputs, General-Purpose I/O (Full Drive Strength)
        5.    Typical Characteristics, General-Purpose I/O (Full Drive Strength)
        6. Table 5-10 Outputs, General-Purpose I/O (Reduced Drive Strength)
        7.    Typical Characteristics, General-Purpose I/O (Reduced Drive Strength)
        8. Table 5-11 Output Frequency, General-Purpose I/O
      5. 5.8.5  Power-Management Module (PMM)
        1. Table 5-12 PMM, Brownout Reset (BOR)
        2. Table 5-13 PMM, Core Voltage
        3. Table 5-14 PMM, SVS High Side
        4. Table 5-15 PMM, SVM High Side
        5. Table 5-16 PMM, SVS Low Side
        6. Table 5-17 PMM, SVM Low Side
      6. 5.8.6  Auxiliary Supplies Module
        1. Table 5-18 Auxiliary Supplies, Recommended Operating Conditions
        2. Table 5-19 Auxiliary Supplies, AUX3 (Backup Subsystem) Currents
        3. Table 5-20 Auxiliary Supplies, Auxiliary Supply Monitor
        4. Table 5-21 Auxiliary Supplies, Switch ON-Resistance
        5. Table 5-22 Auxiliary Supplies, Switching Time
        6. Table 5-23 Auxiliary Supplies, Switch Leakage
        7. Table 5-24 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
        8. Table 5-25 Auxiliary Supplies, Charge-Limiting Resistor
      7. 5.8.7  Timer_A Module
        1. Table 5-26 Timer_A
      8. 5.8.8  eUSCI Module
        1. Table 5-27 eUSCI (UART Mode) Clock Frequency
        2. Table 5-28 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-29 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-30 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-31 eUSCI (SPI Slave Mode)
        6. Table 5-32 eUSCI (I2C Mode)
      9. 5.8.9  LCD Controller
        1. Table 5-33 LCD_C Operating Conditions
        2. Table 5-34 LCD_C Electrical Characteristics
      10. 5.8.10 SD24_B Module
        1. Table 5-35 SD24_B Power Supply and Recommended Operating Conditions
        2. Table 5-36 SD24_B Analog Input
        3. Table 5-37 SD24_B Supply Currents
        4. Table 5-38 SD24_B Performance
        5. Table 5-39 SD24_B AC Performance
        6. Table 5-40 SD24_B AC Performance
        7. Table 5-41 SD24_B AC Performance
        8. Table 5-42 SD24_B External Reference Input
      11. 5.8.11 ADC10_A Module
        1. Table 5-43 10-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-44 10-Bit ADC, Timing Parameters
        3. Table 5-45 10-Bit ADC, Linearity Parameters
        4. Table 5-46 10-Bit ADC, External Reference
      12. 5.8.12 REF Module
        1. Table 5-47 REF, Built-In Reference
      13. 5.8.13 Flash
        1. Table 5-48 Flash Memory
      14. 5.8.14 Emulation and Debug
        1. Table 5-49 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Backup RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power-Management Module (PMM)
      3. 6.11.3  Auxiliary Supply System
      4. 6.11.4  Backup Subsystem
      5. 6.11.5  Digital I/O
      6. 6.11.6  Port Mapping Controller
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  Watchdog Timer (WDT_A)
      9. 6.11.9  DMA Controller
      10. 6.11.10 CRC16
      11. 6.11.11 Hardware Multiplier
      12. 6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)
      13. 6.11.13 ADC10_A
      14. 6.11.14 SD24_B
      15. 6.11.15 TA0
      16. 6.11.16 TA1
      17. 6.11.17 TA2
      18. 6.11.18 TA3
      19. 6.11.19 SD24_B Triggers
      20. 6.11.20 ADC10_A Triggers
      21. 6.11.21 Real-Time Clock (RTC_C)
      22. 6.11.22 Reference (REF) ModuleVoltage Reference
      23. 6.11.23 LCD_C
      24. 6.11.24 Embedded Emulation Module (EEM) (S Version)
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and MSP430F67xxAIPN)
      2. 6.12.2  Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and MSP430F67xxAIPN)
      3. 6.12.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and MSP430F67xxAIPN)
      4. 6.12.4  Port P1 (P1.6 and P1.7) (MSP430F67xxAIPZ and MSP430F67xxAIPN) and Port P2 (P2.0 and P2.1) (MSP430F67xxAIPZ Only) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      6. 6.12.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      7. 6.12.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      8. 6.12.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      9. 6.12.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      10. 6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      11. 6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      12. 6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      13. 6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      14. 6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      15. 6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      16. 6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Memory
      1. 6.14.1 Memory Organization
      2. 6.14.2 Peripheral File Map
    15. 6.15 Identification
      1. 6.15.1 Revision Identification
      2. 6.15.2 Device Identification
      3. 6.15.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Documentation Support

The following documents describe the MSP430F673xA and MSP430F672xA MCUs. Copies of these documents are available on the Internet at

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your device on (see Section 8.5 for links). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document.


User's Guides

    MSP430™ Flash Device Bootloader (BSL) User's Guide

    The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (DSPs) that automatically load program code (and data) from external memory to the internal memory of the DSP.

    MSP430 Programming With the JTAG Interface

    This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).

    MSP430 Hardware Tools User's Guide

    This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the parallel port interface and the USB interface, are described.

Application Reports

    Differences Between MSP430F67xx and MSP430F67xxA Devices

    This application report describes the enhancements of the MSP430F67xxA devices from the non-A MSP430F67xx devices. This application report describes the MSP430F67xx errata that are fixed in the MSP430F67xxA and the additional features added to the MSP430F67xxA devices. In addition, metrology results are compared to further show that the changes implemented in the MSP430F67xxA devices do not affect the metrology performance.

    MSP430 32-kHz Crystal Oscillators

    Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillator operation in mass production.

    MSP430 System-Level ESD Considerations

    System-Level ESD has become increasingly demanding with silicon technology scaling towards lower voltages and the need for designing cost-effective and ultra-low-power components. This application report addresses three different ESD topics to help board designers and OEMs understand and design robust system-level designs.

    Designing With MSP430 and Segment LCDs

    Segment liquid crystal displays (LCDs) are needed to provide information to users in a wide variety of applications from smart meters to electronic shelf labels (ESLs) to medical equipment. Several MSP430™ microcontroller families include built-in low-power LCD driver circuitry that allows the MSP430 MCU to directly control the segmented LCD glass. This application note helps explain how segmented LCDs work, the different features of the various LCD modules across the MSP430 MCU family, LCD hardware layout tips, guidance on writing efficient and easy-to-use LCD driver software, and an overview of the portfolio of MSP430 devices that include different LCD features to aid in device selection.