1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram.
Figure 1-1 Functional Block Diagram
- The MCU has one main power pair of DVCC and DVSS that supplies digital and analog modules. Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with ±5% accuracy.
- VREG is the decoupling capacitor of the CapTIvate regulator. The recommended value for the required decoupling capacitor is 1 µF, with a maximum ESR of ≤200 mΩ.
- P1 and P2 feature the pin interrupt function and can wake the MCU from all LPMs, including LPM3.5 and LPM4.
- Each Timer_A3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected. CCR0 registers can be used only for internal period timing and interrupt generation.
- Each Timer_A2 has two capture/compare registers. Both registers can be used only for internal period timing and interrupt generation.
- In LPM3 mode, the CapTIvate module can be functional while the rest of the peripherals are off.