SLASE35C May 2014 – December 2017 MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729
|CAUTION||These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information.|
|CAUTION||System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturb of data or code memory. See MSP430™ System-Level ESD Considerations for more information.|
The TI MSP430FR572x family of ultra-low-power microcontrollers consists of multiple devices that feature embedded FRAM nonvolatile memory, ultra-low-power 16-bit MSP430™ CPU, and different peripherals targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash, all at lower total power consumption. Peripherals include a 10-bit ADC, a 16-channel comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels capable of I2C, SPI, or UART protocols, an internal DMA, a hardware multiplier, an RTC, five 16-bit timers, and digital I/Os.
|PART NUMBER||PACKAGE||BODY SIZE(2)|
|MSP430FR5729RHA||VQFN (40)||6 mm × 6 mm|
|MSP430FR5729DA||TSSOP (38)||12.5 mm × 6.2 mm|
|MSP430FR5728RGE||VQFN (24)||4 mm × 4 mm|
|MSP430FR5728PW||TSSOP (28)||9.7 mm × 4.4 mm|
Figure 1-1 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and MSP430FR5729 devices in the RHA package. For the functional block diagrams for all device variants and package options, see Section 6.1.