SLASE35 Data sheet

SLASE35C May 2014 – December 2017 MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

DA|38
- MPDS502
RHA|40
- MPQF135D

Thermal pad, mechanical data (Package|Pins)

DA|38
- QFND327
RHA|40
- QFND027R

Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Voltage applied at V_CC to V_SS	–0.3	4.1	V
Voltage applied to any pin (excluding VCORE) ⁽²⁾	–0.3	V_CC + 0.3	V
Diode current at any device pin		±2	mA
Maximum junction temperature, T_J		95	°C
Storage temperatureT_stg⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	–55	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. V_CORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Data retention on FRAM cannot be ensured when exceeding the specified maximum storage temperature, T_stg.

(4) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

(5) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020 specification.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage during program execution and FRAM programming (AVCC = DVCC) ⁽¹⁾		2.0		3.6	V
V_SS	Supply voltage (AVSS = DVSS)			0		V
T_A	Operating free-air temperature		–40		85	°C
T_J	Operating junction temperature		–40		85	°C
C_VCORE	Required capacitor at VCORE⁽²⁾			470		nF
C_VCC/ C_VCORE	Capacitor ratio of VCC to VCORE		10
f_SYSTEM	Processor frequency (maximum MCLK frequency)⁽³⁾	No FRAM wait states⁽⁴⁾, 2 V ≤ V_CC ≤ 3.6 V	0		8.0	MHz

(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.

(2) A capacitor tolerance of ±20% or better is required.

(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(4) When using manual wait state control, see the MSP430FR57xx Family User's Guide for recommended settings for common system frequencies.

5.4 Active Mode Supply Current Into V_CC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)⁽¹⁾ ⁽²⁾ ⁽³⁾

PARAMETER	EXECUTION MEMORY	V_CC	Frequency (f_MCLK = f_SMCLK)						UNIT
			1 MHz		4 MHz		8 MHz
			TYP	MAX	TYP	MAX	TYP	MAX
I_{AM, FRAM_UNI}⁽⁵⁾	FRAM	3 V	0.27		0.58		1.0		mA
I_AM,0%⁽⁶⁾	FRAM 0% cache hit ratio	3 V	0.42	0.73	1.2	1.6	2.2	2.8	mA
I_AM,50%⁽⁶⁾ ⁽⁴⁾	FRAM 50% cache hit ratio	3 V	0.31		0.73		1.3		mA
I_AM,66%⁽⁶⁾ ⁽⁴⁾	FRAM 66% cache hit ratio	3 V	0.27		0.58		1.0		mA
I_AM,75%⁽⁶⁾ ⁽⁴⁾	FRAM 75% cache hit ratio	3 V	0.25		0.5		0.82		mA
I_AM,100%⁽⁶⁾ ⁽⁴⁾	FRAM 100% cache hit ratio	3 V	0.2	0.43	0.3	0.55	0.42	0.8	mA
I_{AM, RAM}⁽⁴⁾ ⁽⁷⁾	RAM	3 V	0.2	0.4	0.35	0.55	0.55	0.75	mA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF.

(3) Characterized with program executing typical data processing.

(4) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data shown in .
f_ACLK = 32786 Hz, f_MCLK = f_SMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

(5) Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK.

(6) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK. No wait states enabled.

(7) All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK.

MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 slas639_IAM_nowait_curves.gif

Figure 5-1 Typical Active Mode Supply Currents, No Wait States

5.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾ ⁽²⁾

PARAMETER		V_CC	–40°C		25°C		60°C		85°C		UNIT
PARAMETER		V_CC	TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX	UNIT
I_LPM0,1MHz	Low-power mode 0 ⁽³⁾ ⁽¹²⁾	2 V, 3 V	166		175		190		225		µA
_LPM0,8MHz	Low-power mode 0 ⁽⁴⁾ ⁽¹²⁾	2 V, 3 V	170		177	244	195		225	360	µA
_LPM0,24MHz	Low-power mode 0 ⁽⁵⁾ ⁽¹²⁾	2 V, 3 V	274		285	340	315		340	455	µA
I_LPM2	Low-power mode 2 ⁽⁶⁾ ⁽¹³⁾	2 V, 3 V	56		61	80	75		110	210	µA
I_LPM3,XT1LF	Low-power mode 3, crystal mode ⁽⁷⁾ ⁽¹³⁾	2 V, 3 V	3.4		6.4	15	18		48	150	µA
I_LPM3,VLO	Low-power mode 3, VLO mode ⁽⁸⁾ ⁽¹³⁾	2 V, 3 V	3.3		6.3	15	18		48	150	µA
I_LPM4	Low-power mode 4 ⁽⁹⁾ ⁽¹³⁾	2 V, 3 V	2.9		5.9	15	18		48	150	µA
I_LPM3.5	Low-power mode 3.5 ⁽¹⁰⁾	2 V, 3 V	1.3		1.5	2.2	1.9		2.8	5.0	µA
I_LPM4.5	Low-power mode 4.5 ⁽¹¹⁾	2 V, 3 V	0.3		0.32	0.66	0.38		0.57	2.55	µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK = 32768 Hz, f_MCLK = 0 MHz, f_SMCLK = 1 MHz. DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz)

(4) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK = 32768 Hz, f_MCLK = 0 MHz, f_SMCLK = 8 MHz. DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz)

(5) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f_ACLK = 32768 Hz, f_MCLK = 0 MHz, f_SMCLK = 24 MHz. DCORSEL = 1, DCOFSELx = 3 (f_DCO = 24 MHz)

(6) Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f_ACLK = 32768 Hz, f_MCLK = 0 MHz, f_SMCLK = f_DCO = 0 MHz, DCORSEL = 0, DCOFSELx = 3, DCO bias generator enabled.

(7) Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK = 32768 Hz, f_MCLK = f_SMCLK = f_DCO = 0 MHz

(8) Current for watchdog timer (clocked by ACLK) included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f_ACLK = f_VLO, f_MCLK = f_SMCLK = f_DCO = 0 MHz

(9) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f_DCO = f_ACLK= f_MCLK = f_SMCLK = 0 MHz

(10) Internal regulator disabled. No data retention. RTC active clocked by XT1 LF mode.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM3.5), f_DCO = f_ACLK= f_MCLK = f_SMCLK = 0 MHz

(11) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f_DCO = f_ACLK= f_MCLK = f_SMCLK = 0 MHz

(12) Current for brownout, high-side supervisor (SVS_H), and low-side supervisor (SVS_L) included.

(13) Current for brownout and high-side supervisor (SVS_H) included. Low-side supervisor (SVS_L) disabled.

5.6 Thermal Resistance Characteristics

PARAMETER		PACKAGE	VALUE⁽¹⁾	UNIT
θ_JA	Junction-to-ambient thermal resistance, still air⁽²⁾	TSSOP-24 (PW)	78.8	°C/W
θ_JC(TOP)	Junction-to-case (top) thermal resistance⁽³⁾		19.4	°C/W
θ_JB	Junction-to-board thermal resistance⁽⁵⁾		36.7	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter		36.2	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter		0.5	°C/W
θ_JC(BOTTOM)	Junction-to-case (bottom) thermal resistance⁽⁴⁾		N/A	°C/W
θ_JA	Junction-to-ambient thermal resistance, still air⁽²⁾	QFN-24 (RGE)	42.1	°C/W
θ_JC(TOP)	Junction-to-case (top) thermal resistance⁽³⁾		38.8	°C/W
θ_JB	Junction-to-board thermal resistance⁽⁵⁾		18.1	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter		18.0	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter		0.6	°C/W
θ_JC(BOTTOM)	Junction-to-case (bottom) thermal resistance⁽⁴⁾		2.8	°C/W
θ_JA	Junction-to-ambient thermal resistance, still air⁽²⁾	SOIC-38 (DA)	74.5	°C/W
θ_JC(TOP)	Junction-to-case (top) thermal resistance⁽³⁾		22.0	°C/W
θ_JB	Junction-to-board thermal resistance⁽⁵⁾		40.7	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter		40.3	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter		0.9	°C/W
θ_JC(BOTTOM)	Junction-to-case (bottom) thermal resistance⁽⁴⁾		N/A	°C/W
θ_JA	Junction-to-ambient thermal resistance, still air⁽²⁾	QFN-40 (RHA)	37.8	°C/W
θ_JC(TOP)	Junction-to-case (top) thermal resistance⁽³⁾		27.4	°C/W
θ_JB	Junction-to-board thermal resistance⁽⁵⁾		12.6	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter		12.6	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter		0.4	°C/W
θ_JC(BOTTOM)	Junction-to-case (bottom) thermal resistance⁽⁴⁾		3.6	°C/W

(1) N/A = Not applicable

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

5.7 Schmitt-Trigger Inputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_IT+	Positive-going input threshold voltage		2 V	0.80		1.40	V
V_IT+	Positive-going input threshold voltage		3 V	1.50		2.10	V
V_IT–	Negative-going input threshold voltage		2 V	0.45		1.10	V
V_IT–	Negative-going input threshold voltage		3 V	0.75		1.65	V
V_hys	Input voltage hysteresis (V_IT+ – V_IT–)		2 V	0.25		0.8	V
V_hys	Input voltage hysteresis (V_IT+ – V_IT–)		3 V	0.30		1.0	V
R_Pull	Pullup or pulldown resistor	For pullup: V_IN = V_SS For pulldown: V_IN = V_CC		20	35	50	kΩ
C_I	Input capacitance	V_IN = V_SS or V_CC			5		pF

5.8 Inputs – Ports P1 and P2 ⁽¹⁾
(P1.0 to P1.7, P2.0 to P2.7)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_(int)	External interrupt timing ⁽²⁾	External trigger pulse duration to set interrupt flag	2 V, 3 V	20		ns

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int) is met. It may be set by trigger signals shorter than t_(int).

5.9 Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
I_lkg(Px.x)	High-impedance leakage current	⁽¹⁾ ⁽²⁾	2 V, 3 V	–50	50	nA

(1) The leakage current is measured with V_SS or V_CC applied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

5.10 Outputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
V_OH	High-level output voltage	I_(OHmax) = –1 mA ⁽¹⁾	2 V	V_CC – 0.25	V_CC	V
		I_(OHmax) = –3 mA ⁽²⁾	2 V	V_CC – 0.60	V_CC
		I_(OHmax) = –2 mA ⁽¹⁾	3 V	V_CC – 0.25	V_CC
		I_(OHmax) = –6 mA ⁽²⁾	3 V	V_CC – 0.60	V_CC
V_OL	Low-level output voltage	I_(OLmax) = 1 mA ⁽¹⁾	2 V	V_SS	V_SS + 0.25	V
		I_(OLmax) = 3 mA ⁽²⁾	2 V	V_SS	V_SS + 0.60
		I_(OLmax) = 2 mA ⁽¹⁾	3 V	V_SS	V_SS + 0.25
		I_(OLmax) = 6 mA ⁽²⁾	3 V	V_SS	V_SS + 0.60

(1) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.

(2) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.

5.11 Output Frequency – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MAX	UNIT
f_Px.y	Port output frequency (with load)	Px.y ⁽¹⁾ ⁽²⁾	2 V	16	MHz
f_Px.y	Port output frequency (with load)	Px.y ⁽¹⁾ ⁽²⁾	3 V	24	MHz
f_{Port_CLK}	Clock output frequency	ACLK, SMCLK, or MCLK at configured output port, C_L = 20 pF, no DC loading ⁽²⁾	2 V	16	MHz
f_{Port_CLK}	Clock output frequency		3 V	24	MHz

(1) A resistive divider with 2 × 1.6 kΩ between V_CC and V_SS is used as load. The output is connected to the center tap of the divider. C_L = 20 pF is connected from the output to V_SS.

(2) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.

5.12 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

V_CC = 2.0 V

Measured at Px.y

Figure 5-2 Typical Low-Level Output Current vs Low-Level Output Voltage

V_CC = 3.0 V

Measured at Px.y

Figure 5-3 Typical Low-Level Output Current vs Low-Level Output Voltage

V_CC = 2.0 V

Measured at Px.y

Figure 5-4 Typical High-Level Output Current vs High-Level Output Voltage

V_CC = 3.0 V

Measured at Px.y

Figure 5-5 Typical High-Level Output Current vs High-Level Output Voltage

5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode ⁽⁵⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
ΔI_VCC.LF	Additional current consumption XT1 LF mode from lowest drive setting	f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {1}, C_L,eff = 9 pF, T_A = 25°C,	3 V		60		nA
		f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {2}, T_A = 25°C, C_L,eff = 9 pF	3 V		90
		f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, T_A = 25°C, C_L,eff = 12 pF	3 V		140
f_XT1,LF0	XT1 oscillator crystal frequency, LF mode	XTS = 0, XT1BYPASS = 0			32768		Hz
f_XT1,LF,SW	XT1 oscillator logic-level square-wave input frequency, LF mode	XTS = 0, XT1BYPASS = 1 ⁽⁶⁾ ⁽⁷⁾		10	32.768	50	kHz
OA_LF	Oscillation allowance for LF crystals ⁽⁸⁾	XTS = 0, XT1BYPASS = 0, XT1DRIVE = {0}, f_XT1,LF = 32768 Hz, C_L,eff = 6 pF			210		kΩ
OA_LF	Oscillation allowance for LF crystals ⁽⁸⁾	XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, f_XT1,LF = 32768 Hz, C_L,eff = 12 pF			300		kΩ
	Duty cycle, LF mode	XTS = 0, Measured at ACLK, f_XT1,LF = 32768 Hz		30%		70%
f_Fault,LF	Oscillator fault frequency, LF mode ⁽⁴⁾	XTS = 0 ⁽³⁾		10		10000	Hz
t_START,LF	Start-up time, LF mode ⁽⁹⁾	f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {0}, T_A = 25°C, C_L,eff = 6 pF	3 V		1000		ms
t_START,LF	Start-up time, LF mode ⁽⁹⁾	f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVE = {3}, T_A = 25°C, C_L,eff = 12 pF	3 V		1000		ms
C_L,eff	Integrated effective load capacitance, LF mode ⁽¹⁾ ⁽²⁾	XTS = 0			1		pF

(1) Requires external capacitors at both terminals.

(2) Values are specified by crystal manufacturers. Include parasitic bond and package capacitance (approximately 2 pF per pin). Recommended values supported are 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.

(5) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(6) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet.

(7) Maximum frequency of operation of the entire device cannot be exceeded.

(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application:

For XT1DRIVE = {0}, C_L,eff ≤ 6 pF.
For XT1DRIVE = {1}, 6 pF ≤ C_L,eff ≤ 9 pF.
For XT1DRIVE = {2}, 6 pF ≤ C_L,eff ≤ 10 pF.
For XT1DRIVE = {3}, 6 pF ≤ C_L,eff ≤ 12 pF.

(9) Includes start-up counter of 4096 clock cycles.

5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode ⁽⁵⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_VCC,HF	XT1 oscillator crystal current HF mode	f_OSC = 4 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {0}, T_A = 25°C, C_L,eff = 16 pF	3 V		175		µA
		f_OSC = 8 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {1}, T_A = 25°C, C_L,eff = 16 pF			300
		f_OSC = 16 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {2}, T_A = 25°C, C_L,eff = 16 pF			350
		f_OSC = 24 MHz, XTS = 1, XOSCOFF = 0, XT1BYPASS = 0, XT1DRIVE = {3}, T_A = 25°C, C_L,eff = 16 pF			550
f_XT1,HF0	XT1 oscillator crystal frequency, HF mode 0	XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0} ⁽⁷⁾		4		6	MHz
f_XT1,HF1	XT1 oscillator crystal frequency, HF mode 1	XTS = 1, XT1BYPASS = 0, XT1DRIVE = {1} ⁽⁷⁾		6		10	MHz
f_XT1,HF2	XT1 oscillator crystal frequency, HF mode 2	XTS = 1, XT1BYPASS = 0, XT1DRIVE = {2} ⁽⁷⁾		10		16	MHz
f_XT1,HF3	XT1 oscillator crystal frequency, HF mode 3	XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3} ⁽⁷⁾		16		24	MHz
f_XT1,HF,SW	XT1 oscillator logic-level square-wave input frequency, HF mode	XTS = 1, XT1BYPASS = 1 ⁽⁶⁾ ⁽⁷⁾		1		24	MHz
OA_HF	Oscillation allowance for HF crystals ⁽⁸⁾	XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0}, f_XT1,HF = 4 MHz, C_L,eff = 16 pF			450		Ω
		XTS = 1, XT1BYPASS = 0, XT1DRIVE = {1}, f_XT1,HF = 8 MHz, C_L,eff = 16 pF			320
		XTS = 1, XT1BYPASS = 0, XT1DRIVE = {2}, f_XT1,HF = 16 MHz, C_L,eff = 16 pF			200
		XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3}, f_XT1,HF = 24 MHz, C_L,eff = 16 pF			200
t_START,HF	Start-up time, HF mode ⁽⁹⁾	f_OSC = 4 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVE = {0}, T_A = 25°C, C_L,eff = 16 pF	3 V		8		ms
t_START,HF	Start-up time, HF mode ⁽⁹⁾	f_OSC = 24 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVE = {3}, T_A = 25°C, C_L,eff = 16 pF	3 V		2		ms
C_L,eff	Integrated effective load capacitance ⁽¹⁾ ⁽²⁾	XTS = 1			1		pF
	Duty cycle, HF mode	XTS = 1, Measured at ACLK, f_XT1,HF2 = 24 MHz		40%	50%	60%
f_Fault,HF	Oscillator fault frequency, HF mode ⁽⁴⁾	XTS = 1 ⁽³⁾		145		900	kHz

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.

(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specificiations might set the flag.

(5) To improve EMI on the XT1 oscillator the following guidelines should be observed.

Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(6) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet.

(7) Maximum frequency of operation of the entire device cannot be exceeded.

(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(9) Includes start-up counter of 4096 clock cycles.

5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_VLO	VLO frequency	Measured at ACLK	2 V to 3.6 V	5	8.3	13	kHz
df_VLO/d_T	VLO frequency temperature drift	Measured at ACLK ⁽¹⁾	2 V to 3.6 V		0.5		%/°C
df_VLO/dV_CC	VLO frequency supply voltage drift	Measured at ACLK ⁽²⁾	2 V to 3.6 V		4		%/V
f_VLO,DC	Duty cycle	Measured at ACLK	2 V to 3.6 V	40%	50%	60%

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(2.0 V to 3.6 V) – MIN(2.0 V to 3.6 V)) / MIN(2.0 V to 3.6 V) / (3.6 V – 2 V)

NOTE

In LPM3, the VLO frequency varies by up to ±6% (typical), due to bias current sampling. This frequency variation is not a violation VLO specifications (see Section 5.15).

5.16 DCO Frequencies

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC T_A	MIN	TYP	MAX	UNIT
f_DCO,LO	DCO frequency low, trimmed	Measured at ACLK, DCORSEL = 0	2 V to 3.6 V –40°C to 85°C		5.37	±3.5%	MHz
f_DCO,LO	DCO frequency low, trimmed	Measured at ACLK, DCORSEL = 0	2 V to 3.6 V 0°C to 50°C		5.37	±2.0%	MHz
f_DCO,MID	DCO frequency mid, trimmed	Measured at ACLK, DCORSEL = 0	2 V to 3.6 V –40°C to 85°C		6.67	±3.5%	MHz
f_DCO,MID	DCO frequency mid, trimmed	Measured at ACLK, DCORSEL = 0	2 V to 3.6 V 0°C to 50°C		6.67	±2.0%	MHz
f_DCO,HI	DCO frequency high, trimmed	Measured at ACLK, DCORSEL = 0	2 V to 3.6 V –40°C to 85°C		8	±3.5%	MHz
f_DCO,HI	DCO frequency high, trimmed	Measured at ACLK, DCORSEL = 0	2 V to 3.6 V 0°C to 50°C		8	±2.0%	MHz
f_DCO,DC	Duty cycle	Measured at ACLK, divide by 1, No external divide, all DCO settings	2 V to 3.6 V –40°C to 85°C	40%	50%	60%

5.17 MODOSC

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_MODOSC	Current consumption	Enabled	2 V to 3.6 V		44	80	µA
f_MODOSC	MODOSC frequency		2 V to 3.6 V	4.5	5.0	5.5	MHz
f_MODOSC,DC	Duty cycle	Measured at ACLK, divide by 1	2 V to 3.6 V	40%	50%	60%

5.18 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_CORE(AM)	Core voltage, active mode	2 V ≤ DV_CC ≤ 3.6 V		1.5		V
V_CORE(LPM)	Core voltage, low-current mode	2 V ≤ DV_CC ≤ 3.6 V		1.5		V

5.19 PMM, SVS, BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_SVSH,AM	SVS_H current consumption, active mode	V_CC = 3.6 V		5		µA
I_SVSH,LPM	SVS_H current consumption, low power modes	V_CC = 3.6 V		0.8	1.5	µA
V_SVSH-	SVS_H on voltage level, falling supply voltage		1.83	1.88	1.93	V
V_SVSH+	SVS_H off voltage level, rising supply voltage		1.88	1.93	1.98	V
t_{PD,SVSH, AM}	SVS_H propagation delay, active mode	dV_CC/dt = 10 mV/µs		10		µs
t_{PD,SVSH, LPM}	SVS_H propagation delay, low power modes	dV_CC/dt = 1 mV/µs		30		µs
I_SVSL	SVS_L current consumption			0.3	0.5	µA
V_SVSL–	SVS_L on voltage level			1.42		V
V_SVSL+	SVS_L off voltage level			1.47		V

5.20 Wake-up Times From Low-Power Modes

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC T_A	MIN	TYP	MAX	UNIT
t_{WAKE-UP LPM0}	Wake-up time from LPM0 to active mode ⁽¹⁾		2 V, 3 V –40°C to 85°C		0.58	1	µs
t_{WAKE-UP LPM12}	Wake-up time from LPM1, LPM2 to active mode ⁽¹⁾		2 V, 3 V –40°C to 85°C		12	25	µs
t_{WAKE-UP LPM34}	Wake-up time from LPM3 or LPM4 to active mode ⁽¹⁾		2 V, 3 V –40°C to 85°C		78	120	µs
t_{WAKE-UP LPMx.5}	Wake-up time from LPM3.5 or LPM4.5 to active mode ⁽¹⁾		2 V, 3 V 0°C to 85°C		310	575	µs
t_{WAKE-UP LPMx.5}	Wake-up time from LPM3.5 or LPM4.5 to active mode ⁽¹⁾		2 V, 3 V –40°C to 85°C		310	1100	µs
t_{WAKE-UP RESET}	Wake-up time from RST to active mode ⁽²⁾	V_CC stable	2 V, 3 V –40°C to 85°C		230	280	µs
t_{WAKE-UP BOR}	Wake-up time from BOR or power-up to active mode	dV_CC/dt = 2400 V/s	2 V, 3 V –40°C to 85°C		1.6		ms
t_RESET	Pulse duration required at RST/NMI terminal to accept a reset event⁽³⁾		2 V, 3 V –40°C to 85°C	4			ns

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed.

(2) The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is executed.

(3) Meeting or exceeding this time makes sures a reset event occurs. Pulses shorter than this minimum time may or may not cause a reset event to occur.

5.21 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_TA	Timer_A input clock frequency	Internal: SMCLK, ACLK External: TACLK Duty cycle = 50% ±10%	2 V, 3 V			8	MHz
t_TA,cap	Timer_A capture timing	All capture inputs, Minimum pulse duration required for capture	2 V, 3 V	20			ns

5.22 Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_TB	Timer_B input clock frequency	Internal: SMCLK, ACLK External: TBCLK Duty cycle = 50% ±10%	2 V, 3 V			8	MHz
t_TB,cap	Timer_B capture timing	All capture inputs, Minimum pulse duration required for capture	2 V, 3 V	20			ns

5.23 eUSCI (UART Mode) Clock Frequency

PARAMETER		CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ±10%				f_SYSTEM	MHz
f_BITCLK	BITCLK clock frequency (equals baud rate in MBaud)					5	MHz

5.24 eUSCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
t_t	UART receive deglitch time⁽¹⁾	UCGLITx = 0	2 V, 3 V	5	15	20	ns
		UCGLITx = 1		20	45	60
		UCGLITx = 2		35	80	120
		UCGLITx = 3		50	110	180

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.25 eUSCI (SPI Master Mode) Clock Frequency

PARAMETER		CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK, ACLK Duty cycle = 50% ±10%				f_SYSTEM	MHz

5.26 eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,LAG	STE lag time, Last clock to STE inactive	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,LAG	STE lag time, Last clock to STE inactive	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,ACC	STE access time, STE active to SIMO data out	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V		55	ns
t_STE,ACC	STE access time, STE active to SIMO data out	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V		35	ns
t_STE,DIS	STE disable time, STE inactive to SIMO high impedance	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SIMO high impedance	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V		30	ns
t_SU,MI	SOMI input data setup time		2 V	35		ns
t_SU,MI	SOMI input data setup time		3 V	35		ns
t_HD,MI	SOMI input data hold time		2 V	0		ns
t_HD,MI	SOMI input data hold time		3 V	0		ns
t_VALID,MO	SIMO output data valid time ⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	2 V		30	ns
t_VALID,MO	SIMO output data valid time ⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	3 V		30	ns
t_HD,MO	SIMO output data hold time ⁽³⁾	C_L = 20 pF	2 V	0		ns
t_HD,MO	SIMO output data hold time ⁽³⁾	C_L = 20 pF	3 V	0		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-6 and Figure 5-7.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-6 and Figure 5-7.

Figure 5-6 SPI Master Mode, CKPH = 0

Figure 5-7 SPI Master Mode, CKPH = 1

5.27 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock		2 V	7		ns
t_STE,LEAD	STE lead time, STE active to clock		3 V	7		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		2 V	0		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		3 V	0		ns
t_STE,ACC	STE access time, STE active to SOMI data out		2 V		65	ns
t_STE,ACC	STE access time, STE active to SOMI data out		3 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		2 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		3 V		35	ns
t_SU,SI	SIMO input data setup time		2 V	2		ns
t_SU,SI	SIMO input data setup time		3 V	2		ns
t_HD,SI	SIMO input data hold time		2 V	5		ns
t_HD,SI	SIMO input data hold time		3 V	5		ns
t_VALID,SO	SOMI output data valid time ⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	2 V		30	ns
t_VALID,SO	SOMI output data valid time ⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	3 V		30	ns
t_HD,SO	SOMI output data hold time ⁽³⁾	C_L = 20 pF	2 V	4		ns
t_HD,SO	SOMI output data hold time ⁽³⁾	C_L = 20 pF	3 V	4		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-8 and Figure 5-9.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-8 and Figure 5-9.

Figure 5-8 SPI Slave Mode, CKPH = 0

Figure 5-9 SPI Slave Mode, CKPH = 1

5.28 eUSCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-10)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ±10%				f_SYSTEM	MHz
f_SCL	SCL clock frequency		2 V, 3 V	0		400	kHz
t_HD,STA	Hold time (repeated) START	f_SCL = 100 kHz	2 V, 3 V	4.0			µs
t_HD,STA	Hold time (repeated) START	f_SCL > 100 kHz	2 V, 3 V	0.6			µs
t_SU,STA	Setup time for a repeated START	f_SCL = 100 kHz	2 V, 3 V	4.7			µs
t_SU,STA	Setup time for a repeated START	f_SCL > 100 kHz	2 V, 3 V	0.6			µs
t_HD,DAT	Data hold time		2 V, 3 V	0			ns
t_SU,DAT	Data setup time		2 V, 3 V	250			ns
t_SU,STO	Setup time for STOP	f_SCL = 100 kHz	2 V, 3 V	4.0			µs
t_SU,STO	Setup time for STOP	f_SCL > 100 kHz	2 V, 3 V	0.6			µs
t_SP	Pulse duration of spikes suppressed by input filter	UCGLITx = 0	2 V, 3 V	50		600	ns
		UCGLITx = 1		25		300
		UCGLITx = 2		12.5		150
		UCGLITx = 3		6.25		75
t_TIMEOUT	Clock low time-out	UCCLTOx = 1	2 V, 3 V		27		ms
		UCCLTOx = 2			30
		UCCLTOx = 3			33

Figure 5-10 I²C Mode Timing

5.29 10-Bit ADC, Power Supply and Input Range Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
AV_CC	Analog supply voltage	AV_CC and DV_CC are connected together, AV_SS and DV_SS are connected together, V_(AVSS) = V_(DVSS) = 0 V		2.0		3.6	V
V_(Ax)	Analog input voltage range	All ADC10 pins		0		AV_CC	V
I_{ADC10_A}	Operating supply current into AVCC terminal, reference current not included	f_ADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0	2 V		90	140	µA
I_{ADC10_A}			3 V		100	160	µA
C_I	Input capacitance	Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad	2.2 V		6	8	pF
R_I	Input MUX ON resistance	AV_CC ≥ 2 V, 0 V ≤ V_Ax ≤ AV_CC				36	kΩ

5.30 10-Bit ADC, Timing Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_ADC10CLK		For specified performance of ADC10 linearity parameters	2 V to 3.6 V	0.45	5	5.5	MHz
f_ADC10OSC	Internal ADC10 oscillator (MODOSC)	ADC10DIV = 0, f_ADC10CLK = f_ADC10OSC	2 V to 3.6 V	4.5	4.5	5.5	MHz
t_CONVERT	Conversion time	REFON = 0, Internal oscillator, 12 ADC10CLK cycles, 10-bit mode, f_ADC10OSC = 4.5 MHz to 5.5 MHz	2 V to 3.6 V	2.18		2.67	µs
t_CONVERT	Conversion time	External f_ADC10CLK from ACLK, MCLK, or SMCLK, ADC10SSEL ≠ 0	2 V to 3.6 V		⁽¹⁾		µs
t_ADC10ON	Turnon settling time of the ADC	The error in a conversion started after t_ADC10ON is less than ±0.5 LSB, Reference and input signal already settled				100	ns
t_Sample	Sampling time	R_S = 1000 Ω, R_I = 36000 Ω, C_I = 3.5 pF, Approximately eight Tau (τ) are required to get an error of less than ±0.5 LSB	2 V	1.5			µs
t_Sample	Sampling time		3 V	2.0			µs

(1) 12 × ADC10DIV × 1/f_ADC10CLK

5.31 10-Bit ADC, Linearity Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
E_I	Integral linearity error	1.4 V ≤ (V_eREF+ – V_REF–/V_eREF–)min ≤ 1.6 V	2 V to 3.6 V	–1.4	1.4	LSB
E_I	Integral linearity error	1.6 V < (V_eREF+ – V_REF–/V_eREF–)min ≤ V_AVCC	2 V to 3.6 V	–1.1	1.1	LSB
E_D	Differential linearity error	(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–)	2 V to 3.6 V	–1	1	LSB
E_O	Offset error	(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–)	2 V to 3.6 V	–6.5	6.5	mV
E_G	Gain error, external reference	(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–)	2 V to 3.6 V	–1.2	1.2	LSB
E_G	Gain error, internal reference ⁽¹⁾			–4%	4%
E_T	Total unadjusted error, external reference	(V_eREF+ – V_REF–/V_eREF–)min ≤ (V_eREF+ – V_REF–/V_eREF–)	2 V to 3.6 V	–2	2	LSB
E_T	Total unadjusted error, internal reference ⁽¹⁾			–4%	4%

(1) Error is dominated by the internal reference.

5.32 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
V_eREF+	Positive external reference voltage input	V_eREF+ > V_eREF– ⁽²⁾		1.4	AV_CC	V
V_eREF–	Negative external reference voltage input	V_eREF+ > V_eREF– ⁽³⁾		0	1.2	V
(V_eREF+ – V_REF–/V_eREF–)	Differential external reference voltage input	V_eREF+ > V_eREF– ⁽⁴⁾		1.4	AV_CC	V
I_VeREF+, I_VeREF–	Static input current	1.4 V ≤ V_eREF+ ≤ V_AVCC, V_eREF– = 0 V, f_ADC10CLK = 5 MHz, ADC10SHTx = 1h, Conversion rate 200 ksps	2.2 V, 3 V	–6	6	µA
I_VeREF+, I_VeREF–	Static input current	1.4 V ≤ V_eREF+ ≤ V_AVCC, V_eREF– = 0 V, f_ADC10CLK = 5 MHz, ADC10SHTx = 8h, Conversion rate 20 ksps	2.2 V, 3 V	–1	1	µA
C_VREF+, C_VREF-	Capacitance at VREF+ or VREF- terminal⁽⁵⁾			10		µF

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_i, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_B. Also see the MSP430FR57xx Family User's Guide.

5.33 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_REF+	Positive built-in reference voltage output	REFVSEL = {2} for 2.5 V, REFON = 1	3 V	2.4	2.5	2.6	V
		REFVSEL = {1} for 2 V, REFON = 1	3 V	1.92	2.0	2.08
		REFVSEL = {0} for 1.5 V, REFON = 1	3 V	1.44	1.5	1.56
AV_CC(min)	AVCC minimum voltage, Positive built-in reference active	REFVSEL = {0} for 1.5 V		2.0			V
		REFVSEL = {1} for 2 V		2.2
		REFVSEL = {2} for 2.5 V		2.7
I_REF+	Operating supply current into AVCC terminal ⁽¹⁾	f_ADC10CLK = 5 MHz, REFON = 1, REFBURST = 0	3 V		33	45	µA
T_REF+	Temperature coefficient of built-in reference	REFVSEL = (0, 1, 2}, REFON = 1			±35		ppm/ °C
PSRR_DC	Power supply rejection ratio (DC)	AV_CC = AV_CC _(min) - AV_CC(max), T_A= 25°C, REFON = 1, REFVSEL = (0} for 1.5 V			1600		µV/V
		AV_CC = AV_CC _(min) - AV_CC(max), T_A= 25°C, REFON = 1, REFVSEL = (1} for 2 V			1900
		AV_CC = AV_CC _(min) - AV_CC(max), T_A= 25°C, REFON = 1, REFVSEL = (2} for 2.5 V			3600
t_SETTLE	Settling time of reference voltage ⁽²⁾	AV_CC = AV_CC _(min) - AV_CC(max), REFVSEL = (0, 1, 2}, REFON = 0 → 1			30		µs

(1) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.

(2) The condition is that the error in a conversion started after t_REFON is less than ±0.5 LSB.

5.34 REF, Temperature Sensor and Built-In V_MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_SENSOR	See ⁽¹⁾	ADC10ON = 1, INCH = 0Ah, T_A = 0°C	2 V, 3 V		790		mV
TC_SENSOR		ADC10ON = 1, INCH = 0Ah	2 V, 3 V		2.55		mV/°C
t_{SENSOR(sample)}	Sample time required if channel 10 is selected ⁽²⁾	ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB	2 V	30			µs
t_{SENSOR(sample)}	Sample time required if channel 10 is selected ⁽²⁾	ADC10ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB	3 V	30			µs
V_MID	AV_CC divider at channel 11	ADC10ON = 1, INCH = 0Bh, V_MID is ~0.5 × V_AVCC	2 V	0.97	1.0	1.03	V
V_MID	AV_CC divider at channel 11	ADC10ON = 1, INCH = 0Bh, V_MID is ~0.5 × V_AVCC	3 V	1.46	1.5	1.54	V
t_VMID(sample)	Sample time required if channel 11 is selected ⁽³⁾	ADC10ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB	2 V, 3 V	1000			ns

(1) The temperature sensor offset can vary significantly. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor.

(2) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on).

(3) The on-time t_VMID(on) is included in the sampling time t_VMID(sample); no additional on time is needed.

Figure 5-11 Typical Temperature Sensor Voltage

5.35 Comparator_D

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_pd	Propagation delay, AVCC = 2 V to 3.6 V	Overdrive = 10 mV, VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV)	50	100	200	ns
		Overdrive = 100 mV, VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV)		80
		Overdrive = 250 mV, (VIN+ – 400 mV) to (VIN+ + 250 mV)		50
t_filter	Filter timer added to the propagation delay of the comparator	CDF = 1, CDFDLY = 00	0.3	0.5	0.9	µs
		CDF = 1, CDFDLY = 01	0.5	0.9	1.5
		CDF = 1, CDFDLY = 10	0.9	1.6	2.8
		CDF = 1, CDFDLY = 11	1.6	3.0	5.5
V_offset	Input offset	AVCC = 2 V to 3.6 V	–20		20	mV
V_ic	Common mode input range	AVCC = 2 V to 3.6 V	0		AVCC - 1	V
I_comp(AVCC)	Comparator only	CDON = 1, AVCC = 2 V to 3.6 V		29	34	µA
I_ref(AVCC)	Reference buffer and R‑ladder	CDREFLx = 01, AVCC = 2 V to 3.6 V		20	24	µA
t_enable,comp	Comparator enable time	CDON = 0 to CDON = 1, AVCC = 2 V to 3.6 V		1.1	2.0	µs
t_{enable,rladder}	Resistor ladder enable time	CDON = 0 to CDON = 1, AVCC = 2 V to 3.6 V		1.1	2.0	µs
V_{CB_REF}	Reference voltage for a tap	VIN = voltage input to the R-ladder, n = 0 to 31	VIN × (n + 0.5) / 32	VIN × (n + 1) / 32	VIN × (n + 1.5) / 32	V

5.36 FRAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
DV_CC(WRITE)	Write supply voltage		2.0	3.6	V
t_WRITE	Word or byte write time			120	ns
t_ACCESS	Read access time ⁽¹⁾			60	ns
t_PRECHARGE	Precharge time ⁽¹⁾			60	ns
t_CYCLE	Cycle time, read or write operation ⁽¹⁾		120		ns
	Read and write endurance		10¹⁵		cycles
t_Retention	Data retention duration	T_J = 25°C	100		years
		T_J = 70°C	40
		T_J = 85°C	10

(1) When using manual wait state control, see the MSP430FR57xx Family User's Guide for recommended settings for common system frequencies.

5.37 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		V_CC	MIN	TYP	MAX	UNIT
f_SBW	Spy-Bi-Wire input frequency	2 V, 3 V	0		20	MHz
t_SBW,Low	Spy-Bi-Wire low clock pulse duration	2 V, 3 V	0.025		15	µs
t_{SBW, En}	Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) ⁽¹⁾	2 V, 3 V			1	µs
t_SBW,Rst	Spy-Bi-Wire return to normal operation time		19		35	µs
f_TCK	TCK input frequency, 4-wire JTAG ⁽²⁾	2 V	0		5	MHz
f_TCK	TCK input frequency, 4-wire JTAG ⁽²⁾	3 V	0		10	MHz
R_internal	Internal pulldown resistance on TEST	2 V, 3 V	20	35	50	kΩ

(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the t_SBW,En time after the first transition of the TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence.

(2) f_TCK may be restricted to meet the timing requirements of the module selected.

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Active Mode Supply Current Into VCC Excluding External Current

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

5.6 Thermal Resistance Characteristics

5.7 Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

5.8 Inputs – Ports P1 and P2 (1) (P1.0 to P1.7, P2.0 to P2.7)

5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

5.10 Outputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

5.11 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

5.12 Typical Characteristics – Outputs

5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode (5)

5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode (5)

5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

5.16 DCO Frequencies

5.17 MODOSC

5.18 PMM, Core Voltage

5.19 PMM, SVS, BOR

5.20 Wake-up Times From Low-Power Modes

5.21 Timer_A

5.22 Timer_B

5.23 eUSCI (UART Mode) Clock Frequency

5.24 eUSCI (UART Mode)

5.25 eUSCI (SPI Master Mode) Clock Frequency

5.26 eUSCI (SPI Master Mode)

5.27 eUSCI (SPI Slave Mode)

5.28 eUSCI (I2C Mode)

5.29 10-Bit ADC, Power Supply and Input Range Conditions

5.30 10-Bit ADC, Timing Parameters

5.31 10-Bit ADC, Linearity Parameters

5.32 REF, External Reference

5.33 REF, Built-In Reference

5.34 REF, Temperature Sensor and Built-In VMID

5.35 Comparator_D

5.36 FRAM

5.37 JTAG and Spy-Bi-Wire Interface

5.1 Absolute Maximum Ratings⁽¹⁾

5.4 Active Mode Supply Current Into V_CC Excluding External Current

5.5 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

5.7 Schmitt-Trigger Inputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

5.8 Inputs – Ports P1 and P2 ⁽¹⁾
(P1.0 to P1.7, P2.0 to P2.7)

5.9 Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)

5.10 Outputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

5.11 Output Frequency – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)

5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode ⁽⁵⁾

5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode ⁽⁵⁾

5.28 eUSCI (I²C Mode)

5.34 REF, Temperature Sensor and Built-In V_MID