SLASEF5B January   2019  – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431


  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. Brownout and Device Reset Power Ramp Requirements
        2. SVS
      2. 8.13.2  Reset Timing
        1. Reset Input
      3. 8.13.3  Clock Specifications
        1. Low-Frequency Crystal Oscillator, LFXT
        2. High-Frequency Crystal Oscillator, HFXT
        3. DCO
        4. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. Wake-up Times From Low-Power Modes and Reset
        2. Typical Wake-up Charges
        3. Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. Digital Inputs
        2. Digital Outputs
        3. Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. Timer_A
        2. Timer_B
      8. 8.13.8  eUSCI
        1. eUSCI (UART Mode) Clock Frequency
        2. eUSCI (UART Mode) Switching Characteristics
        3. eUSCI (SPI Master Mode) Clock Frequency
        4. eUSCI (SPI Master Mode) Switching Characteristics
        5. eUSCI (SPI Master Mode) Timing Diagrams
        6. eUSCI (SPI Slave Mode) Switching Characteristics
        7. eUSCI (SPI Slave Mode) Timing Diagrams
        8. eUSCI (I2C Mode) Switching Characteristics
        9. eUSCI (SPI Slave Mode) Timing Diagrams
      9. 8.13.9  Segment LCD Controller
        1. LCD_C Recommended Operating Conditions
        2. LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 12-Bit ADC, Power Supply and Input Range Conditions
        2. 12-Bit ADC, Timing Parameters
        3. 12-Bit ADC, Linearity Parameters
        4. 12-Bit ADC, Dynamic Performance With External Reference
        5. 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 12-Bit ADC, External Reference
        8. Temperature Sensor Typical Characteristics
      11. 8.13.11 Reference
        1. REF, Built-In Reference
      12. 8.13.12 Comparator
        1. Comparator_E
      13. 8.13.13 FRAM
        1. FRAM Memory
      14. 8.13.14 USS
        1. USS Recommended Operating Conditions
        2. USS LDO
        3. USSXTAL
        4. USS HSPLL
        5. USS SDHS
        6. USS PHY Output Stage
        7. USS PHY Input Stage, Multiplexer
        8. USS_PGA
        9. USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS_A)
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Measurement Test Interface (MTIF)
      7. 9.13.7  Watchdog Timer (WDT_A)
      8. 9.13.8  System Module (SYS)
      9. 9.13.9  DMA Controller
      10. 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 9.13.11 TA0, TA1, and TA4
      12. 9.13.12 TA2 and TA3
      13. 9.13.13 TB0
      14. 9.13.14 ADC12_B
      15. 9.13.15 USS_A
      16. 9.13.16 Comparator_E
      17. 9.13.17 CRC16
      18. 9.13.18 CRC32
      19. 9.13.19 AES256 Accelerator
      20. 9.13.20 True Random Seed
      21. 9.13.21 Shared Reference (REF)
      22. 9.13.22 LCD_C
      23. 9.13.23 Embedded Emulation
        1. Embedded Emulation Module (EEM) (S Version)
        2. EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.5) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.0 to P2.1) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P2 (P2.2 to P2.3) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P2 (P2.4 to P2.5) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P2 (P2.6 to P2.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P3 (P3.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P3 (P3.1) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P3 (P3.2) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P3 (P3.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P3 (P3.4 to P3.5) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P3 (P3.6 to P3.7) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P4 (P4.0) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P4 (P4.1 to P4.7) Input/Output With Schmitt Trigger
      17. 9.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      18. 9.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger
      19. 9.14.19 Port P6 (P6.1 to P6.2) Input/Output With Schmitt Trigger
      20. 9.14.20 Port P6 (P6.3) Input/Output With Schmitt Trigger
      21. 9.14.21 Port P6 (P6.4) Input/Output With Schmitt Trigger
      22. 9.14.22 Port P6 (P6.5 and P6.7) Input/Output With Schmitt Trigger
      23. 9.14.23 Port P7 (P7.0) Input/Output With Schmitt Trigger
      24. 9.14.24 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      25. 9.14.25 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      26. 9.14.26 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. Partial Schematic
        2. Design Requirements
        3. Detailed Design Procedure
        4. Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. Partial Schematic
        2. Design Requirements
        3. Detailed Design Procedure
        4. Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
    9. 11.9 Export Control Notice
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Peripheral File Map

For complete module register descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

Table 9-53 Peripherals
Special Functions (see Table 9-54) 0100h 011Fh
PMM (see Table 9-55) 0120h 013Fh
FRAM Control (see Table 9-56) 0140h 014Fh
CRC (see Table 9-57) 0150h 0157h
RAM Control (see Table 9-58) 0158h 0159h
Watchdog (see Table 9-59) 015Ch 015Dh
CS (see Table 9-60) 0160h 016Fh
SYS (see Table 9-61) 0180h 019Fh
Shared Reference (see Table 9-62) 01B0h 01B1h
Digital I/O (see Table 9-63) 0200h 033Fh
TA0 (see Table 9-64) 0340h 036Fh
TA1 (see Table 9-65) 0380h 03AFh
TB0 (see Table 9-66) 03C0h 03EFh
TA2 (see Table 9-67) 0400h 042Fh
TA3 (see Table 9-68) 0440h 046Fh
RTC_C (see Table 9-69) 04A0h 04BFh
32-bit Hardware Multiplier (see Table 9-70) 04C0h 04EFh
DMA (see Table 9-71) 0500h 056Fh
MPU Control (see Table 9-72) 05A0h 05AFh
eUSCI_A0 (see Table 9-73) 05C0h 05DFh
eUSCI_A1 (see Table 9-74) 05E0h 05FFh
eUSCI_A2 (see Table 9-75) 0600h 061Fh
eUSCI_A3 (see Table 9-76) 0620h 063Fh
eUSCI_B0 (see Table 9-77) 0640h 066Fh
eUSCI_B1 (see Table 9-78) 0680h 06AFh
TA4 (see Table 9-79) 07C0h 07EFh
ADC12_B (see Table 9-80) 0800h 089Fh
Comparator E (see Table 9-81) 08C0h 08CFh
CRC32 (see Table 9-82) 0980h 09AFh
AES256 (see Table 9-83) 09C0h 09CFh
LCD_C (see Table 9-90) 0A00h 0A5Fh
LEA (see Table 9-84) 0A80h 0AFFh
SAPH_A (see Table 9-85) 0E00h 0E7Fh
SDHS (see Table 9-86) 0E80h 0EBFh
UUPS (see Table 9-87) 0EC0h 0EDFh
HSPLL (see Table 9-88) 0EE0h 0EFFh
MTIF (see Table 9-89) 0F00h 0F1Fh
Table 9-54 Special Functions Registers
Interrupt Enable SFRIE1 0100h
Interrupt Flag SFRIFG1 0102h
Reset Pin Control SFRRPCR 0104h
Table 9-55 PMM Registers
PMM control register 0 PMMCTL0 0120h
PMM interrupt flag register PMMIFG 012Ah
Power mode 5 control register 0 PM5CTL0 0130h
Table 9-56 FRAM Control Registers
FRAM Controller A Control Register 0 FRCTL0 0140h
General Control Register 0 GCCTL0 0144h
General Control Register 1 GCCTL1 0146h
Table 9-57 CRC Registers
CRC Data In CRCDI 0150h
CRC Data In Reverse Byte CRCDIRB 0152h
CRC Initialization and Result CRCINIRES 0154h
CRC Result Reverse CRCRESR 0156h
Table 9-58 RAM Control Registers
RAM Controller Control 0 RCCTL0 0158h
RAM Controller Control 1 RCCTL1 015Ah
Table 9-59 Watchdog Registers
Watchdog Timer Control Register WDTCTL 015Ch
Table 9-60 CS Registers
Clock System Control 0 CSCTL0 0160h
Clock System Control 1 CSCTL1 0162h
Clock System Control 2 CSCTL2 0164h
Clock System Control 3 CSCTL3 0166h
Clock System Control 4 CSCTL4 0168h
Clock System Control 5 CSCTL5 016Ah
Clock System Control 6 CSCTL6 016Ch
Table 9-61 SYS Registers
System Control SYSCTL 0180h
JTAG Mailbox Control SYSJMBC 0186h
JTAG Mailbox Input SYSJMBI0 0188h
JTAG Mailbox Input SYSJMBI1 018Ah
JTAG Mailbox Output SYSJMBO0 018Ch
JTAG Mailbox Output SYSJMBO1 018Eh
User NMI Vector Generator SYSUNIV 019Ah
System NMI Vector Generator SYSSNIV 019Ch
Reset Vector Generator SYSRSTIV 019Eh
Table 9-62 Shared Reference Registers
REF Control Register 0 REFCTL0 01B0h
Table 9-63 Digital I/O Registers
Port A Input PAIN 0200h
Port 1 Input P1IN 0200h
Port 2 Input P2IN 0201h
Port A Output PAOUT 0202h
Port 1 Output P1OUT 0202h
Port 2 Output P2OUT 0203h
Port A Direction PADIR 0204h
Port 1 Direction P1DIR 0204h
Port 2 Direction P2DIR 0205h
Port A Resistor Enable PAREN 0206h
Port 1 Resistor Enable P1REN 0206h
Port 2 Resistor Enable P2REN 0207h
Port A Select 0 PASEL0 020Ah
Port 1 Select 0 P1SEL0 020Ah
Port 2 Select 0 P2SEL0 020Bh
Port A Select 1 PASEL1 020Ch
Port 1 Select 1 P1SEL1 020Ch
Port 2 Select 1 P2SEL1 020Dh
Port 1 Interrupt Vector Register P1IV 020Eh
Port A Complement Select PASELC 0216h
Port 1 Complement Select P1SELC 0216h
Port 2 Complement Select P2SELC 0217h
Port A Interrupt Edge Select PAIES 0218h
Port 1 Interrupt Edge Select P1IES 0218h
Port 2 Interrupt Edge Select P2IES 0219h
Port A Interrupt Enable PAIE 021Ah
Port 1 Interrupt Enable P1IE 021Ah
Port 2 Interrupt Enable P2IE 021Bh
Port A Interrupt Flag PAIFG 021Ch
Port 1 Interrupt Flag P1IFG 021Ch
Port 2 Interrupt Flag P2IFG 021Dh
Port 2 Interrupt Vector Register P2IV 021Eh
Port B Input PBIN 0220h
Port 3 Input P3IN 0220h
Port 4 Input P4IN 0221h
Port B Output PBOUT 0222h
Port 3 Output P3OUT 0222h
Port 4 Output P4OUT 0223h
Port B Direction PBDIR 0224h
Port 3 Direction P3DIR 0224h
Port 4 Direction P4DIR 0225h
Port B Resistor Enable PBREN 0226h
Port 3 Resistor Enable P3REN 0226h
Port 4 Resistor Enable P4REN 0227h
Port B Select 0 PBSEL0 022Ah
Port 3 Select 0 P3SEL0 022Ah
Port 4 Select 0 P4SEL0 022Bh
Port B Select 1 PBSEL1 022Ch
Port 3 Select 1 P3SEL1 022Ch
Port 4 Select 1 P4SEL1 022Dh
Port 3 Interrupt Vector Register P3IV 022Eh
Port B Complement Select PBSELC 0236h
Port 3 Complement Select P3SELC 0236h
Port 4 Complement Select P4SELC 0237h
Port B Interrupt Edge Select PBIES 0238h
Port 3 Interrupt Edge Select P3IES 0238h
Port 4 Interrupt Edge Select P4IES 0239h
Port B Interrupt Enable PBIE 023Ah
Port 3 Interrupt Enable P3IE 023Ah
Port 4 Interrupt Enable P4IE 023Bh
Port B Interrupt Flag PBIFG 023Ch
Port 3 Interrupt Flag P3IFG 023Ch
Port 4 Interrupt Flag P4IFG 023Dh
Port 4 Interrupt Vector Register P4IV 023Eh
Port C Input PCIN 0240h
Port 5 Input P5IN 0240h
Port 6 Input P6IN 0241h
Port C Output PCOUT 0242h
Port 5 Output P5OUT 0242h
Port 6 Output P6OUT 0243h
Port C Direction PCDIR 0244h
Port 5 Direction P5DIR 0244h
Port 6 Direction P6DIR 0245h
Port C Resistor Enable PCREN 0246h
Port 5 Resistor Enable P5REN 0246h
Port 6 Resistor Enable P6REN 0247h
Port C Select 0 PCSEL0 024Ah
Port 5 Select 0 P5SEL0 024Ah
Port 6 Select 0 P6SEL0 024Bh
Port C Select 1 PCSEL1 024Ch
Port 5 Select 1 P5SEL1 024Ch
Port 6 Select 1 P6SEL1 024Dh
Port 5 Interrupt Vector Register P5IV 024Eh
Port C Complement Select PCSELC 0256h
Port 5 Complement Select P5SELC 0256h
Port 6 Complement Select P6SELC 0257h
Port C Interrupt Edge Select PCIES 0258h
Port 5 Interrupt Edge Select P5IES 0258h
Port 6 Interrupt Edge Select P6IES 0259h
Port C Interrupt Enable PCIE 025Ah
Port 5 Interrupt Enable P5IE 025Ah
Port 6 Interrupt Enable P6IE 025Bh
Port C Interrupt Flag PCIFG 025Ch
Port 5 Interrupt Flag P5IFG 025Ch
Port 6 Interrupt Flag P6IFG 025Dh
Port 6 Interrupt Vector Register P6IV 025Eh
Port D Input PDIN 0260h
Port 7 Input P7IN 0260h
Port D Output PDOUT 0262h
Port 7 Output P7OUT 0262h
Port D Direction PDDIR 0264h
Port 7 Direction P7DIR 0264h
Port D Resistor Enable PDREN 0266h
Port 7 Resistor Enable P7REN 0266h
Port D Select 0 PDSEL0 026Ah
Port 7 Select 0 P7SEL0 026Ah
Port D Select 1 PDSEL1 026Ch
Port 7 Select 1 P7SEL1 026Ch
Port 7 Interrupt Vector Register P7IV 026Eh
Port D Complement Select PDSELC 0276h
Port 7 Complement Select P7SELC 0276h
Port D Interrupt Edge Select PDIES 0278h
Port 7 Interrupt Edge Select P7IES 0278h
Port D Interrupt Enable PDIE 027Ah
Port 7 Interrupt Enable P7IE 027Ah
Port D Interrupt Flag PDIFG 027Ch
Port 7 Interrupt Flag P7IFG 027Ch
Port J Input PJIN 0320h
Port J Output PJOUT 0322h
Port J Direction PJDIR 0324h
Port J Resistor Enable PJREN 0326h
Port J Select 0 PJSEL0 032Ah
Port J Select 1 PJSEL1 032Ch
Port J Complement Select PJSELC 0336h
Table 9-64 TA0 Registers
Timer_A0 Control Register TA0CTL 0340h
Timer_A0 Capture/Compare Control Register TA0CCTL0 0342h
Timer_A0 Capture/Compare Control Register TA0CCTL1 0344h
Timer_A0 Capture/Compare Control Register TA0CCTL2 0346h
Timer_A0 register TA0R 0350h
Timer_A0 Capture/Compare Register TA0CCR0 0352h
Timer_A0 Capture/Compare Register TA0CCR1 0354h
Timer_A0 Capture/Compare Register TA0CCR2 0356h
Timer_A0 Expansion 0 Register TA0EX0 0360h
Timer_A0 Interrupt Vector Register TA0IV 036Eh
Table 9-65 TA1 Registers
Timer_A1 Control Register TA1CTL 0380h
Timer_A1 Capture/Compare Control Register TA1CCTL0 0382h
Timer_A1 Capture/Compare Control Register TA1CCTL1 0384h
Timer_A1 Capture/Compare Control Register TA1CCTL2 0386h
Timer_A1 register TA1R 0390h
Timer_A1 Capture/Compare Register TA1CCR0 0392h
Timer_A1 Capture/Compare Register TA1CCR1 0394h
Timer_A1 Capture/Compare Register TA1CCR2 0396h
Timer_A1 Expansion 0 Register TA1EX0 03A0h
Timer_A1 Interrupt Vector Register TA1IV 03AEh
Table 9-66 TB0 Registers
Timer_B0 Control Register TB0CTL 03C0h
Timer_B0 Capture/Compare Control Register TB0CCTL0 03C2h
Timer_B0 Capture/Compare Control Register TB0CCTL1 03C4h
Timer_B0 Capture/Compare Control Register TB0CCTL2 03C6h
Timer_B0 Capture/Compare Control Register TB0CCTL3 03C8h
Timer_B0 Capture/Compare Control Register TB0CCTL4 03CAh
Timer_B0 Capture/Compare Control Register TB0CCTL5 03CCh
Timer_B0 Capture/Compare Control Register TB0CCTL6 03CEh
Timer_B0 count register TB0R 03D0h
Timer_B0 Capture/Compare Register TB0CCR0 03D2h
Timer_B0 Capture/Compare Register TB0CCR1 03D4h
Timer_B0 Capture/Compare Register TB0CCR2 03D6h
Timer_B0 Capture/Compare Register TB0CCR3 03D8h
Timer_B0 Capture/Compare Register TB0CCR4 03DAh
Timer_B0 Capture/Compare Register TB0CCR5 03DCh
Timer_B0 Capture/Compare Register TB0CCR6 03DEh
Timer_B0 Expansion Register 0 TB0EX0 03E0h
Timer_B0 Interrupt Vector Register TB0IV 03EEh
Table 9-67 TA2 Registers
Timer_A2 Control Register TA2CTL 0400h
Timer_A2 Capture/Compare Control Register TA2CCTL0 0402h
Timer_A2 Capture/Compare Control Register TA2CCTL1 0404h
Timer_A2 register TA2R 0410h
Timer_A2 Capture/Compare Register TA2CCR0 0412h
Timer_A2 Capture/Compare Register TA2CCR1 0414h
Timer_A2 Expansion 0 Register TA2EX0 0420h
Timer_A2 Interrupt Vector Register TA2IV 042Eh
Table 9-68 TA3 Registers
Timer_A3 Control Register TA3CTL 0440h
Timer_A3 Capture/Compare Control Register TA3CCTL0 0442h
Timer_A3 Capture/Compare Control Register TA3CCTL1 0444h
Timer_A3 register TA3R 0450h
Timer_A3 Capture/Compare Register TA3CCR0 0452h
Timer_A3 Capture/Compare Register TA3CCR1 0454h
Timer_A3 Expansion 0 Register TA3EX0 0460h
Timer_A3 Interrupt Vector Register TA3IV 046Eh
Table 9-69 RTC_C Registers
RTCCTL0 Register RTCCTL0 04A0h
RTCCTL13 Register RTCCTL13 04A2h
Real-Time Clock Prescale Timer 0 Control Register RTCPS0CTL 04A8h
Real-Time Clock Prescale Timer 1 Control Register RTCPS1CTL 04AAh
Real-Time Clock Prescale Timer Counter Register RTCPS 04ACh
Prescale timer 0 counter value RT0PS 04ACh
Prescale timer 1 counter value RT1PS 04ADh
Real-Time Clock Interrupt Vector Register RTCIV 04AEh
RTCTIM0 Register – Hexadecimal Format RTCTIM0 04B0h
Real-Time Clock Hour, Day of Week RTCTIM1 04B2h
RTCDATE - Hexadecimal Format RTCDATE 04B4h
RTCYEAR Register – Hexadecimal Format RTCYEAR 04B6h
RTCMINHR - Hexadecimal Format RTCAMINHR 04B8h
RTCADOWDAY - Hexadecimal Format RTCADOWDAY 04BAh
Binary-to-BCD Conversion Register BIN2BCD 04BCh
BCD-to-Binary Conversion Register BCD2BIN 04BEh
Table 9-70 32-bit Hardware Multiplier Registers
16-bit operand one – multiply MPY 04C0h
16-bit operand one – signed multiply MPYS 04C2h
16-bit operand one – multiply accumulate MAC 04C4h
16-bit operand one – signed multiply accumulate MACS 04C6h
16-bit operand two OP2 04C8h
16x16-bit result low word RESLO 04CAh
16x16-bit result high word RESHI 04CCh
16x16-bit sum extension register SUMEXT 04CEh
32-bit operand 1 – multiply – low word MPY32L 04D0h
32-bit operand 1 – multiply – high word MPY32H 04D2h
32-bit operand 1 – signed multiply – low word MPYS32L 04D4h
32-bit operand 1 – signed multiply – high word MPYS32H 04D6h
32-bit operand 1 – multiply accumulate – low word MAC32L 04D8h
32-bit operand 1 – multiply accumulate – high word MAC32H 04DAh
32-bit operand 1 – signed multiply accumulate – low word MACS32L 04DCh
32-bit operand 1 – signed multiply accumulate – high word MACS32H 04DEh
32-bit operand 2 – low word OP2L 04E0h
32-bit operand 2 – high word OP2H 04E2h
32x32-bit result 0 – least significant word RES0 04E4h
32x32-bit result 1 RES1 04E6h
32x32-bit result 2 RES2 04E8h
32x32-bit result 3 – most significant word RES3 04EAh
MPY32 control register 0 MPY32CTL0 04ECh
Table 9-71 DMA Registers
DMA Control 0 DMACTL0 0500h
DMA Control 1 DMACTL1 0502h
DMA Control 2 DMACTL2 0504h
DMA Control 4 DMACTL4 0508h
DMA Interrupt Vector DMAIV 050Eh
DMA Channel 0 Control DMA0CTL 0510h
DMA Channel 0 Source Address DMA0SA 0512h
DMA Channel 0 Destination Address DMA0DA 0516h
DMA Channel 0 Transfer Size DMA0SZ 051Ah
DMA Channel 1 Control DMA1CTL 0520h
DMA Channel 1 Source Address DMA1SA 0522h
DMA Channel 1 Destination Address DMA1DA 0526h
DMA Channel 1 Transfer Size DMA1SZ 052Ah
DMA Channel 2 Control DMA2CTL 0530h
DMA Channel 2 Source Address DMA2SA 0532h
DMA Channel 2 Destination Address DMA2DA 0536h
DMA Channel 2 Transfer Size DMA2SZ 053Ah
DMA Channel 3 Control DMA3CTL 0540h
DMA Channel 3 Source Address DMA3SA 0542h
DMA Channel 3 Destination Address DMA3DA 0546h
DMA Channel 3 Transfer Size DMA3SZ 054Ah
DMA Channel 4 Control DMA4CTL 0550h
DMA Channel 4 Source Address DMA4SA 0552h
DMA Channel 4 Destination Address DMA4DA 0556h
DMA Channel 4 Transfer Size DMA4SZ 055Ah
DMA Channel 5 Control DMA5CTL 0560h
DMA Channel 5 Source Address DMA5SA 0562h
DMA Channel 5 Destination Address DMA5DA 0566h
DMA Channel 5 Transfer Size DMA5SZ 056Ah
Table 9-72 MPU Control Registers
Memory Protection Unit Control 0 MPUCTL0 05A0h
Memory Protection Unit Control 1 MPUCTL1 05A2h
Memory Protection Unit Segmentation Border 2 Register MPUSEGB2 05A4h
Memory Protection Unit Segmentation Border 1 Register MPUSEGB1 05A6h
Memory Protection Unit Segmentation Access Management Register MPUSAM 05A8h
Memory Protection Unit IP Control 0 Register MPUIPC0 05AAh
Memory Protection Unit IP Encapsulation Segment Border 2 Register MPUIPSEGB2 05ACh
Memory Protection Unit IP Encapsulation Segment Border 1 Register MPUIPSEGB1 05AEh
Table 9-73 eUSCI_A0 Registers
eUSCI_A0 Control Word Register 0 UCA0CTLW0 05C0h
eUSCI_A0 Control Word Register 1 UCA0CTLW1 05C2h
eUSCI_A0 Baud Rate Control Word Register UCA0BRW 05C6h
eUSCI_A0 Modulation Control Word Register UCA0MCTLW 05C8h
eUSCI_A0 Status Register UCA0STATW 05CAh
eUSCI_A0 Receive Buffer Register UCA0RXBUF 05CCh
eUSCI_A0 Transmit Buffer Register UCA0TXBUF 05CEh
eUSCI_A0 Auto Baud Rate Control Register UCA0ABCTL 05D0h
eUSCI_A0 IrDA Control Word Register UCA0IRCTL 05D2h
eUSCI_A0 Interrupt Enable Register UCA0IE 05DAh
eUSCI_A0 Interrupt Flag Register UCA0IFG 05DCh
eUSCI_A0 Interrupt Vector Register UCA0IV 05DEh
Table 9-74 eUSCI_A1 Registers
eUSCI_A1 Control Word Register 0 UCA1CTLW0 05E0h
eUSCI_A1 Control Word Register 1 UCA1CTLW1 05E2h
eUSCI_A1 Baud Rate Control Word Register UCA1BRW 05E6h
eUSCI_A1 Modulation Control Word Register UCA1MCTLW 05E8h
eUSCI_A1 Status Register UCA1STATW 05EAh
eUSCI_A1 Receive Buffer Register UCA1RXBUF 05ECh
eUSCI_A1 Transmit Buffer Register UCA1TXBUF 05EEh
eUSCI_A1 Auto Baud Rate Control Register UCA1ABCTL 05F0h
eUSCI_A1 IrDA Control Word Register UCA1IRCTL 05F2h
eUSCI_A1 Interrupt Enable Register UCA1IE 05FAh
eUSCI_A1 Interrupt Flag Register UCA1IFG 05FCh
eUSCI_A1 Interrupt Vector Register UCA1IV 05FEh
Table 9-75 eUSCI_A2 Registers
eUSCI_A2 Control Word Register 0 UCA2CTLW0 0600h
eUSCI_A2 Control Word Register 1 UCA2CTLW1 0602h
eUSCI_A2 Baud Rate Control Word Register UCA2BRW 0606h
eUSCI_A2 Modulation Control Word Register UCA2MCTLW 0608h
eUSCI_A2 Status Register UCA2STATW 060Ah
eUSCI_A2 Receive Buffer Register UCA2RXBUF 060Ch
eUSCI_A2 Transmit Buffer Register UCA2TXBUF 060Eh
eUSCI_A2 Auto Baud Rate Control Register UCA2ABCTL 0610h
eUSCI_A2 IrDA Control Word Register UCA2IRCTL 0612h
eUSCI_A2 Interrupt Enable Register UCA2IE 061Ah
eUSCI_A2 Interrupt Flag Register UCA2IFG 061Ch
eUSCI_A2 Interrupt Vector Register UCA2IV 061Eh
Table 9-76 eUSCI_A3 Registers
eUSCI_A3 Control Word Register 0 UCA3CTLW0 0620h
eUSCI_A3 Control Word Register 1 UCA3CTLW1 0622h
eUSCI_A3 Baud Rate Control Word Register UCA3BRW 0626h
eUSCI_A3 Modulation Control Word Register UCA3MCTLW 0628h
eUSCI_A3 Status Register UCA3STATW 062Ah
eUSCI_A3 Receive Buffer Register UCA3RXBUF 062Ch
eUSCI_A3 Transmit Buffer Register UCA3TXBUF 062Eh
eUSCI_A3 Auto Baud Rate Control Register UCA3ABCTL 0630h
eUSCI_A3 IrDA Control Word Register UCA3IRCTL 0632h
eUSCI_A3 Interrupt Enable Register UCA3IE 063Ah
eUSCI_A3 Interrupt Flag Register UCA3IFG 063Ch
eUSCI_A3 Interrupt Vector Register UCA3IV 063Eh
Table 9-77 eUSCI_B0 Registers
eUSCI_B0 Control Word Register 0 UCB0CTLW0 0640h
eUSCI_B0 Control Word Register 1 UCB0CTLW1 0642h
eUSCI_B0 Baud Rate Control Word Register UCB0BRW 0646h
eUSCI_B0 Status Register UCB0STATW 0648h
eUSCI_B0 Byte Counter Threshold Register UCB0TBCNT 064Ah
eUSCI_B0 Receive Buffer Register UCB0RXBUF 064Ch
eUSCI_B0 Transmit Buffer Register UCB0TXBUF 064Eh
eUSCI_B0 I2C Own Address 0 Register UCB0I2COA0 0654h
eUSCI_B0 I2C Own Address 1 Register UCB0I2COA1 0656h
eUSCI_B0 I2C Own Address 2 Register UCB0I2COA2 0658h
eUSCI_B0 I2C Own Address 3 Register UCB0I2COA3 065Ah
eUSCI_B0 I2C Received Address Register UCB0ADDRX 065Ch
eUSCI_B0 I2C Address Mask Register UCB0ADDMASK 065Eh
eUSCI_B0 I2C Slave Address Register UCB0I2CSA 0660h
eUSCI_B0 Interrupt Enable Register UCB0IE 066Ah
eUSCI_B0 Interrupt Flag Register UCB0IFG 066Ch
eUSCI_B0 Interrupt Vector Register UCB0IV 066Eh
Table 9-78 eUSCI_B1 Registers
eUSCI_B1 Control Word Register 0 UCB1CTLW0 0680h
eUSCI_B1 Control Word Register 1 UCB1CTLW1 0682h
eUSCI_B1 Baud Rate Control Word Register UCB1BRW 0686h
eUSCI_B1 Status Register UCB1STATW 0688h
eUSCI_B1 Byte Counter Threshold Register UCB1TBCNT 068Ah
eUSCI_B1 Receive Buffer Register UCB1RXBUF 068Ch
eUSCI_B1 Transmit Buffer Register UCB1TXBUF 068Eh
eUSCI_B1 I2C Own Address 0 Register UCB1I2COA0 0694h
eUSCI_B1 I2C Own Address 1 Register UCB1I2COA1 0696h
eUSCI_B1 I2C Own Address 2 Register UCB1I2COA2 0698h
eUSCI_B1 I2C Own Address 3 Register UCB1I2COA3 069Ah
eUSCI_B1 I2C Received Address Register UCB1ADDRX 069Ch
eUSCI_B1 I2C Address Mask Register UCB1ADDMASK 069Eh
eUSCI_B1 I2C Slave Address Register UCB1I2CSA 06A0h
eUSCI_B1 Interrupt Enable Register UCB1IE 06AAh
eUSCI_B1 Interrupt Flag Register UCB1IFG 06ACh
eUSCI_B1 Interrupt Vector Register UCB1IV 06AEh
Table 9-79 TA4 Registers
Timer_A4 Control Register TA4CTL 07C0h
Timer_A4 Capture/Compare Control Register TA4CCTL0 07C2h
Timer_A4 Capture/Compare Control Register TA4CCTL1 07C4h
Timer_A4 register TA4R 07D0h
Timer_A4 Capture/Compare Register TA4CCR0 07D2h
Timer_A4 Capture/Compare Register TA4CCR1 07D4h
Timer_A4 Expansion 0 Register TA4EX0 07E0h
Timer_A4 Interrupt Vector Register TA4IV 07EEh
Table 9-80 ADC12_B Registers
ADC12_B Control 0 ADC12CTL0 0800h
ADC12_B Control 1 ADC12CTL1 0802h
ADC12_B Control 2 ADC12CTL2 0804h
ADC12_B Control 3 ADC12CTL3 0806h
ADC12_B Window Comparator Low Threshold Register ADC12LO 0808h
ADC12_B Window Comparator High Threshold Register ADC12HI 080Ah
ADC12_B Interrupt Flag 0 ADC12IFGR0 080Ch
ADC12_B Interrupt Flag 1 ADC12IFGR1 080Eh
ADC12_B Interrupt Flag 2 ADC12IFGR2 0810h
ADC12_B Interrupt Enable 0 ADC12IER0 0812h
ADC12_B Interrupt Enable 1 ADC12IER1 0814h
ADC12_B Interrupt Enable 2 ADC12IER2 0816h
ADC12_B Interrupt Vector ADC12IV 0818h
ADC12_B Memory Control 0 Register ADC12MCTL0 0820h
ADC12_B Memory Control 1 Register ADC12MCTL1 0822h
ADC12_B Memory Control 2 Register ADC12MCTL2 0824h
ADC12_B Memory Control 3 Register ADC12MCTL3 0826h
ADC12_B Memory Control 4 Register ADC12MCTL4 0828h
ADC12_B Memory Control 5 Register ADC12MCTL5 082Ah
ADC12_B Memory Control 6 Register ADC12MCTL6 082Ch
ADC12_B Memory Control 7 Register ADC12MCTL7 082Eh
ADC12_B Memory Control 8 Register ADC12MCTL8 0830h
ADC12_B Memory Control 9 Register ADC12MCTL9 0832h
ADC12_B Memory Control 10 Register ADC12MCTL10 0834h
ADC12_B Memory Control 11 Register ADC12MCTL11 0836h
ADC12_B Memory Control 12 Register ADC12MCTL12 0838h
ADC12_B Memory Control 13 Register ADC12MCTL13 083Ah
ADC12_B Memory Control 14 Register ADC12MCTL14 083Ch
ADC12_B Memory Control 15 Register ADC12MCTL15 083Eh
ADC12_B Memory Control 16 Register ADC12MCTL16 0840h
ADC12_B Memory Control 17 Register ADC12MCTL17 0842h
ADC12_B Memory Control 18 Register ADC12MCTL18 0844h
ADC12_B Memory Control 19 Register ADC12MCTL19 0846h
ADC12_B Memory Control 20 Register ADC12MCTL20 0848h
ADC12_B Memory Control 21 Register ADC12MCTL21 084Ah
ADC12_B Memory Control 22 Register ADC12MCTL22 084Ch
ADC12_B Memory Control 23 Register ADC12MCTL23 084Eh
ADC12_B Memory Control 24 Register ADC12MCTL24 0850h
ADC12_B Memory Control 25 Register ADC12MCTL25 0852h
ADC12_B Memory Control 26 Register ADC12MCTL26 0854h
ADC12_B Memory Control 27 Register ADC12MCTL27 0856h
ADC12_B Memory Control 28 Register ADC12MCTL28 0858h
ADC12_B Memory Control 29 Register ADC12MCTL29 085Ah
ADC12_B Memory Control 30 Register ADC12MCTL30 085Ch
ADC12_B Memory Control 31 Register ADC12MCTL31 085Eh
ADC12_B Memory 0 Register ADC12MEM0 0860h
ADC12_B Memory 1 Register ADC12MEM1 0862h
ADC12_B Memory 2 Register ADC12MEM2 0864h
ADC12_B Memory 3 Register ADC12MEM3 0866h
ADC12_B Memory 4 Register ADC12MEM4 0868h
ADC12_B Memory 5 Register ADC12MEM5 086Ah
ADC12_B Memory 6 Register ADC12MEM6 086Ch
ADC12_B Memory 7 Register ADC12MEM7 086Eh
ADC12_B Memory 8 Register ADC12MEM8 0870h
ADC12_B Memory 9 Register ADC12MEM9 0872h
ADC12_B Memory 10 Register ADC12MEM10 0874h
ADC12_B Memory 11 Register ADC12MEM11 0876h
ADC12_B Memory 12 Register ADC12MEM12 0878h
ADC12_B Memory 13 Register ADC12MEM13 087Ah
ADC12_B Memory 14 Register ADC12MEM14 087Ch
ADC12_B Memory 15 Register ADC12MEM15 087Eh
ADC12_B Memory 16 Register ADC12MEM16 0880h
ADC12_B Memory 17 Register ADC12MEM17 0882h
ADC12_B Memory 18 Register ADC12MEM18 0884h
ADC12_B Memory 19 Register ADC12MEM19 0886h
ADC12_B Memory 20 Register ADC12MEM20 0888h
ADC12_B Memory 21 Register ADC12MEM21 088Ah
ADC12_B Memory 22 Register ADC12MEM22 088Ch
ADC12_B Memory 23 Register ADC12MEM23 088Eh
ADC12_B Memory 24 Register ADC12MEM24 0890h
ADC12_B Memory 25 Register ADC12MEM25 0892h
ADC12_B Memory 26 Register ADC12MEM26 0894h
ADC12_B Memory 27 Register ADC12MEM27 0896h
ADC12_B Memory 28 Register ADC12MEM28 0898h
ADC12_B Memory 29 Register ADC12MEM29 089Ah
ADC12_B Memory 30 Register ADC12MEM30 089Ch
ADC12_B Memory 31 Register ADC12MEM31 089Eh
Table 9-81 Comparator E Registers
Comparator Control Register 0 CECTL0 08C0h
Comparator Control Register 1 CECTL1 08C2h
Comparator Control Register 2 CECTL2 08C4h
Comparator Control Register 3 CECTL3 08C6h
Comparator Interrupt Control Register CEINT 08CCh
Comparator Interrupt Vector Word Register CEIV 08CEh
Table 9-82 CRC32 Registers
CRC32 Data Input Word 0 CRC32DIW0 0980h
CRC32 Data Input Word 1 CRC32DIW1 0982h
CRC32 Data In Reverse Word 1 CRC32DIRBW1 0984h
CRC32 Data In Reverse Word 0 CRC32DIRBW0 0986h
CRC32 Initialization and Result Word 0 CRC32INIRESW0 0988h
CRC32 Initialization and Result Word 1 CRC32INIRESW1 098Ah
CRC32 Result Reverse Word 1 CRC32RESRW1 098Ch
CRC32 Result Reverse Word 0 CRC32RESRW0 098Eh
CRC16 Data Input CRC16DIW0 0990h
CRC16 Data In Reverse CRC16DIRBW0 0996h
CRC16 Init and Result CRC16INIRESW0 0998h
CRC16 Result Reverse CRC16RESRW0 099Eh
Table 9-83 AES256 Registers
AES Accelerator Control Register 0 AESACTL0 09C0h
AES Accelerator Control Register 1 AESACTL1 09C2h
AES Accelerator Status Register AESASTAT 09C4h
AES Accelerator Key Register AESAKEY 09C6h
AES Accelerator Data In Register AESADIN 09C8h
AES Accelerator Data Out Register AESADOUT 09CAh
AES Accelerator XORed Data In Register AESAXDIN 09CCh
AES Accelerator XORed Data In Register AESAXIN 09CEh
Table 9-84 LEA Registers
LEA Capability Register LEACAP 0A80h
Configuration Register 0 LEACNF0 0A84h
Configuration Register 1 LEACNF1 0A88h
Configuration Register 2 LEACNF2 0A8Ch
Memory Bottom Register LEAMB 0A90h
Memory Top Register LEAMT 0A94h
Code Memory Access Register LEACMA 0A98h
Code Memory Control Register LEACMCTL 0A9Ch
LEA Command Status Register LEACMDSTAT 0AA8h
LEA Source 1 Status Register LEAS1STAT 0AACh
LEA Source 0 Status Register LEAS0STAT 0AB0h
LEA Result Status Register LEADSTSTAT 0AB4h
PM Control Register LEAPMCTL 0AC0h
PM Result Register LEAPMDST 0AC4h
PM Source 1 Register LEAPMS1 0AC8h
PM Source 0 Register LEAPMS0 0ACCh
PM Command Buffer Register LEAPMCB 0AD0h
Interrupt Flag and Set Register LEAIFGSET 0AF0h
Interrupt Enable Register LEAIE 0AF4h
Interrupt Flag and Clear Register LEAIFG 0AF8h
Interrupt Vector Register LEAIV 0AFCh
Table 9-85 SAPH_A Registers
Interrupt Index SAPH_AIIDX 0E00h
Masked Interrupt Satus SAPH_AMIS 0E02h
Raw Interrupt Status SAPH_ARIS 0E04h
Interrupt Mask SAPH_AIMSC 0E06h
Interrupt Clear SAPH_AICR 0E08h
Interrupt Set SAPH_AISR 0E0Ah
Module-Descriptor Low Word SAPH_ADESCLO 0E0Ch
Module-Descriptor High Word SAPH_ADESCHI 0E0Eh
Physical Interface Output Control #0 SAPH_AOCTL0 0E12h
Physical Interface Output Control #1 SAPH_AOCTL1 0E14h
Physical Interface Output Function Select SAPH_AOSEL 0E16h
Channel 0 Pull UpTrim Register SAPH_ACH0PUT 0E20h
Channel 0 Pull DownTrim Register SAPH_ACH0PDT 0E22h
Channel 0 Termination Trim SAPH_ACH0TT 0E24h
Channel 1 Pull UpTrim SAPH_ACH1PUT 0E26h
Channel 1 Pull DownTrim SAPH_ACH1PDT 0E28h
Channel 1 Termination Trim SAPH_ACH1TT 0E2Ah
Mode Configuration SAPH_AMCNF 0E2Ch
Trim Access Control SAPH_ATACTL 0E2Eh
Physical Interface Input Control #0 SAPH_AICTL0 0E30h
Bias Control SAPH_ABCTL 0E34h
Pulse Generator Low Period SAPH_APGLPER 0E42h
Pulse Generator High Period SAPH_APGHPER 0E44h
PPG Software Trigger SAPH_APPGTRIG 0E48h
Extended Pulse Control Register SAPH_AXPGCTL 0E4Ah
Extra Pulse Low Period Register SAPH_AXPGLPER 0E4Ch
Extra Pulse High Period Register SAPH_AXPGHPER 0E4Eh
A-SEQ control register 0 SAPH_AASCTL0 0E60h
A-SEQ control register 1 SAPH_AASCTL1 0E62h
ASQ Software Trigger SAPH_AASQTRIG 0E64h
ASQ ping output polarity SAPH_AAPOL 0E66h
ASQ ping pause level SAPH_AAPLEV 0E68h
ASQ ping pause impedance SAPH_AAPHIZ 0E6Ah
A-SEQ start to 1st ping SAPH_AATM_A 0E6Eh
ASQ start to ADC arm SAPH_AATM_B 0E70h
Count for the TIMEMARK C Event SAPH_AATM_C 0E72h
ASQ start to ADC trig SAPH_AATM_D 0E74h
ASQ start to restart SAPH_AATM_E 0E76h
ASQ start to timeout SAPH_AATM_F 0E78h
Time Base Control SAPH_ATBCTL 0E7Ah
Acquisition Timer Low Part SAPH_AATIMLO 0E7Ch
Acquisition Timer High Part SAPH_AATIMHI 0E7Eh
Table 9-86 SDHS Registers
Interrupt Index Register SDHSIIDX 0E80h
Masked Interrupt Status and Clear Register SDHSMIS 0E82h
Raw Interrupt Status Register SDHSRIS 0E84h
Interrupt Mask Register SDHSIMSC 0E86h
Interrupt Clear Register. SDHSICR 0E88h
Interrupt Set Register. SDHSISR 0E8Ah
SDHS Descriptor Register L. SDHSDESCLO 0E8Ch
SDHS Descriptor Register H. SDHSDESCHI 0E8Eh
SDHS Control Register 0 SDHSCTL0 0E90h
SDHS Control Register 1 SDHSCTL1 0E92h
SDHS Control Register 2 SDHSCTL2 0E94h
SDHS Control Register 3 SDHSCTL3 0E96h
SDHS Control Register 4 SDHSCTL4 0E98h
SDHS Control Register 5 SDHSCTL5 0E9Ah
SDHS Control Register 6 SDHSCTL6 0E9Ch
SDHS Control Register 7 SDHSCTL7 0E9Eh
SDHS Data Converstion Register SDHSDT 0EA2h
SDHS Window Comparator High Threshold Register. SDHSWINHITH 0EA4h
SDHS Window Comparator Low Threshold Register. SDHSWINLOTH 0EA6h
DTC destination address register SDHSDTCDA 0EA8h
Table 9-87 UUPS Registers
Interrupt Index Register UUPSIIDX 0EC0h
Masked Interrupt Status Register UUPSMIS 0EC2h
Raw Interrupt Status Register UUPSRIS 0EC4h
Interrupt Mask Register UUPSIMSC 0EC6h
Interrupt Clear Register. UUPSICR 0EC8h
Interrupt Flag Set Register. UUPSISR 0ECAh
UUPS Descriptor Register L. UUPSDESCLO 0ECCh
UUPS Descriptor Register H. UUPSDESCHI 0ECEh
Table 9-88 HSPLL Registers
Interrupt Index Register HSPLLIIDX 0EE0h
Masked Interrupt Status Register. HSPLLMIS 0EE2h
Raw Interrupt Status Register HSPLLRIS 0EE4h
Interrupt Mask Register HSPLLIMSC 0EE6h
Interrupt Flag Clear Register. HSPLLICR 0EE8h
Interrupt Flag Set Register. HSPLLISR 0EEAh
HSPLL Descriptor Register L. HSPLLDESCLO 0EECh
HSPLL Descriptor Register H. HSPLLDESCHI 0EEEh
HSPLL Control Register HSPLLCTL 0EF0h
Table 9-89 MTIF Registers
Pulse Generator Configuration Register MTIFPGCNF 0F00h
Pulse Generator Value Register MTIFPGKVAL 0F02h
Pulse Generator Control Register MTIFPGCTL 0F04h
Pulse Generator Status Register MTIFPGSR 0F06h
Pulse Counter Configuration Register MTIFPCCNF 0F08h
Pulse Counter Value Register MTIFPCR 0F0Ah
Pulse Counter Control Register MTIFPCCTL 0F0Ch
Pulse Counter Status Register MTIFPCSR 0F0Eh
Measurement Test Port Control Register MTIFTPCTL 0F10h
Table 9-90 LCD_C Registers
LCD_C control 0 LCDCCTL0 0A00h
LCD_C control 1 LCDCCTL1 0A02h
LCD_C blinking control LCDCBLKCTL 0A04h
LCD_C memory control LCDCMEMCTL 0A06h
LCD_C voltage control LCDCVCTL 0A08h
LCD_C port control 0 LCDCPCTL0 0A0Ah
LCD_C port control 1 LCDCPCTL1 0A0Ch
LCD_C port control 2 (≥256 segments) LCDCPCTL2 0A0Eh
LCD_C port control 3 (384 segments) LCDCPCTL3 0A10h
LCD_C charge pump control register LCDCCPCTL 0A12h
LCD_C interrupt vector LCDCIV 0A1Eh
Static and 2 to 4 mux modes
LCD_C memory 1 LCDM1 0A20h
LCD_C memory 2 LCDM2 0A21h
LCD_C memory 3 LCDM3 0A22h
LCD_C memory 4 LCDM4 0A23h
LCD_C memory 5 LCDM5 0A24h
LCD_C memory 6 LCDM6 0A25h
LCD_C memory 7 LCDM7 0A26h
LCD_C memory 8 LCDM8 0A27h
LCD_C memory 9 LCDM9 0A28h
LCD_C memory 10 LCDM10 0A29h
LCD_C memory 11 LCDM11 0A2Ah
LCD_C memory 12 LCDM12 0A2Bh
LCD_C memory 13 LCDM13 0A2Ch
LCD_C memory 14 LCDM14 0A2Dh
LCD_C memory 15 LCDM15 0A2Eh
LCD_C memory 16 LCDM16 0A2Fh
LCD_C memory 17 LCDM17 0A30h
LCD_C memory 18 LCDM18 0A31h
LCD_C memory 19 LCDM19 0A32h
LCD_C memory 20 LCDM20 0A33h
Reserved 0A34h to 0A3Bh
LCD_C blinking memory 1 LCDBM1 0A40h
LCD_C blinking memory 2 LCDBM2 0A41h
LCD_C blinking memory 3 LCDBM3 0A42h
LCD_C blinking memory 4 LCDBM4 0A43h
LCD_C blinking memory 5 LCDBM5 0A44h
LCD_C blinking memory 6 LCDBM6 0A45h
LCD_C blinking memory 7 LCDBM7 0A46h
LCD_C blinking memory 8 LCDBM8 0A47h
LCD_C blinking memory 9 LCDBM9 0A48h
LCD_C blinking memory 10 LCDBM10 0A49h
LCD_C blinking memory 11 LCDBM11 0A4Ah
LCD_C blinking memory 12 LCDBM12 0A4Bh
LCD_C blinking memory 13 LCDBM13 0A4Ch
LCD_C blinking memory 14 LCDBM14 0A4Dh
LCD_C blinking memory 15 LCDBM15 0A4Eh
LCD_C blinking memory 16 LCDBM16 0A4Fh
LCD_C blinking memory 17 LCDBM17 0A50h
LCD_C blinking memory 18 LCDBM18 0A51h
LCD_C blinking memory 19 LCDBM19 0A52h
LCD_C blinking memory 20 LCDBM20 0A53h
Reserved 0A54h to 0A5Bh
5 to 8 mux modes
LCD_C memory 1 LCDM1 0A20h
LCD_C memory 2 LCDM2 0A21h
LCD_C memory 3 LCDM3 0A22h
LCD_C memory 4 LCDM4 0A23h
LCD_C memory 5 LCDM5 0A24h
LCD_C memory 6 LCDM6 0A25h
LCD_C memory 7 LCDM7 0A26h
LCD_C memory 8 LCDM8 0A27h
LCD_C memory 9 LCDM9 0A28h
LCD_C memory 10 LCDM10 0A29h
LCD_C memory 11 LCDM11 0A2Ah
LCD_C memory 12 LCDM12 0A2Bh
LCD_C memory 13 LCDM13 0A2Ch
LCD_C memory 14 LCDM14 0A2Dh
LCD_C memory 15 LCDM15 0A2Eh
LCD_C memory 16 LCDM16 0A2Fh
LCD_C memory 17 LCDM17 0A30h
LCD_C memory 18 LCDM18 0A31h
LCD_C memory 19 LCDM19 0A32h
LCD_C memory 20 LCDM20 0A33h
LCD_C memory 21 LCDM21 0A34h
LCD_C memory 22 LCDM22 0A35h
LCD_C memory 23 LCDM23 0A36h
LCD_C memory 24 LCDM24 0A37h
LCD_C memory 25 LCDM25 0A38h
LCD_C memory 26 LCDM26 0A39h
LCD_C memory 27 LCDM27 0A3Ah
LCD_C memory 28 LCDM28 0A3Bh
LCD_C memory 29 LCDM29 0A3Ch
LCD_C memory 30 LCDM30 0A3Dh
LCD_C memory 31 LCDM31 0A3Eh
LCD_C memory 32 LCDM32 0A3Fh
LCD_C memory 33 LCDM33 0A40h
LCD_C memory 34 LCDM34 0A41h
LCD_C memory 35 LCDM35 0A42h
LCD_C memory 36 LCDM36 0A43h
Reserved 0A44h to 0A53h

LDC memory is implemented for groups of segments. Memory for non-existent segment lines is accessible but cannot be used.