over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
|fPy.x||Port output frequency (with load)||Py.x, CL = 20 pF, RL = 3.2 kΩ (1) (2)||3 V||16.384||MHz|
|fPort_CLK||Clock output frequency||Py.x, CL = 20 pF(2)||3 V||16.384||MHz|
(1) A resistive divider with two times 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% of VCC at the specified toggle frequency.