SLASF59A May   2023  – December 2023 MSPM0L1304-Q1 , MSPM0L1305-Q1 , MSPM0L1306-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 COMP
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 OPA
      1. 7.17.1 Electrical Characteristics
      2. 7.17.2 Switching Characteristics
      3. 7.17.3 PGA Mode
    18. 7.18 I2C
      1. 7.18.1 I2C Characteristics
      2. 7.18.2 I2C Filter
      3. 7.18.3 I2C Timing Diagram
    19. 7.19 SPI
      1. 7.19.1 SPI
      2. 7.19.2 SPI Timing Diagram
    20. 7.20 UART
    21. 7.21 TIMx
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 CRC
    17. 8.17 GPAMP
    18. 8.18 OPA
    19. 8.19 I2C
    20. 8.20 SPI
    21. 8.21 UART
    22. 8.22 WWDT
    23. 8.23 Timers (TIMx)
    24. 8.24 Device Analog Connections
    25. 8.25 Input/Output Diagrams
    26. 8.26 Serial Wire Debug Interface
    27. 8.27 Bootstrap Loader (BSL)
    28. 8.28 Device Factory Constants
    29. 8.29 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • DYY|16
  • RGE|24
  • RHB|32
  • DGS|32
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

The following table describes the functions available on every pin for each device package.

Note: Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1 Pin Attributes
PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE
ANALOG DIGITAL (1) 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT
N/A N/A VDD 4 7 7 3 6 5 Power
N/A N/A VSS 5 8 8 4 7 6 Power
N/A N/A VCORE 32 3 3 23 3 2 Power
1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4](Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain
2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3](Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain
N/A N/A NRST 3 6 6 2 Reset(2)
3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard
4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard
5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard
6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed
7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard
8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard
9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard
10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard
11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed
12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard
13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard
14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard
15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard
16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard
17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard
18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake
N/A OPA1_IN0-
N/A N/A OPA1_IN0- – – – – 13 – Analog
19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4](BSL Invoke) 22 25 21 14 14 10 Standard with wake
20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed
21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard
22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard
23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5](Default BSL UART_RX) 26 29 25 18 17 13 Standard
24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5](Default BSL UART_TX) 27 30 26 19 18 14 Standard
25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard
N/A N/A OPA0_IN0- – – – – 19 – Analog
26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard
27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard
28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard
(1) PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits.
(2) Reset PIN is muxed with PA1 for 16-pin and 20-pin devices.
Table 6-2 Digital IO Features by IO Type
IO STRUCTUREINVERSION CONTROLDRIVE STRENGTH CONTROLHYSTERESIS CONTROLPULLUP RESISTORPULLDOWN RESISTORWAKEUP LOGIC
Standard driveYYY
Standard drive with wakeYYYY
High speedYYYY
5-V tolerant open drainYYYY