SBAS803A November   2016  – November 2017 MUX506 , MUX507

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Dual Supply
    6. 6.6 Electrical Characteristics: Single Supply
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  Truth Tables
    2. 7.2  On-Resistance
    3. 7.3  Off Leakage
    4. 7.4  On-Leakage Current
    5. 7.5  Transition Time
    6. 7.6  Break-Before-Make Delay
    7. 7.7  Turn-On and Turn-Off Time
    8. 7.8  Charge Injection
    9. 7.9  Off Isolation
    10. 7.10 Channel-to-Channel Crosstalk
    11. 7.11 Bandwidth
    12. 7.12 THD + Noise
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Ultralow Leakage Current
      2. 8.3.2 Ultralow Charge Injection
      3. 8.3.3 Bidirectional Operation
      4. 8.3.4 Rail-to-Rail Operation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The MUX50x are a family of analog multiplexers. The Functional Block Diagram section provides a top-level block diagram of both the MUX506 and MUX507. The MUX506 is a 16-channel, single-ended, analog mux. The MUX507 is an 8-channel, differential or dual 8:1, single-ended, analog mux. Each channel is turned on or turned off based on the state of the address lines and enable pin.

8.2 Functional Block Diagram

MUX506 MUX507 FBD_BAS803.gif

8.3 Feature Description

8.3.1 Ultralow Leakage Current

The MUX50x provide extremely low on- and off-leakage currents. The MUX50x are capable of switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error because of the ultra-low leakage currents. Figure 37 shows typical leakage currents of the MUX50x versus temperature.

MUX506 MUX507 D006_SLASED9.gif Figure 37. Leakage Current vs Temperature

8.3.2 Ultralow Charge Injection

The MUX50x have a simple transmission gate topology, as shown in Figure 38. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

MUX506 MUX507 Transmission_Gate_LASED9.gif Figure 38. Transmission Gate Topology

The MUX50x have special charge-injection cancellation circuitry that reduces the source-to-drain charge injection to as low as 0.31 pC at VS = 0 V, and ±0.9 pC in the full signal range, as shown in Figure 39.

MUX506 MUX507 D011_SLASED9.gif Figure 39. Source-to-Drain Charge Injection

The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux), where D becomes the input and Sx becomes the output. Figure 40 shows the drain-to-source charge injection across the full signal range.

MUX506 MUX507 D008_SLASED9.gif Figure 40. Drain-to-Source Charge Injection

8.3.3 Bidirectional Operation

The MUX50x are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins of the MUX50x are used either as input or output. Each MUX50x channel has very similar characteristics in both directions.

8.3.4 Rail-to-Rail Operation

The valid analog signal for the MUX50x ranges from VSS to VDD. The input signal to the MUX50x swings from VSS to VDD without any significant degradation in performance. The on-resistance of the MUX50x varies with input signal, as shown in Figure 41

MUX506 MUX507 D001_SLASED9.gif Figure 41. On-resistance vs Source or Drain Voltage

8.4 Device Functional Modes

When the EN pin of the MUX50x is pulled high, one of the switches is closed based on the state of the address lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the address lines. The EN pin can be connected to VDD (as high as 36 V).