SPRS586J June   2009  – January 2017 OMAP-L138


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. ARM Internal Memories
        2. External Memories
        3. DSP Internal Memories
        4. C674x CPU
    5. 3.5 Memory Map Summary
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Pin Multiplexing Control
    8. 3.8 Terminal Functions
      1. 3.8.1  Device Reset, NMI and JTAG
      2. 3.8.2  High-Frequency Oscillator and PLL
      3. 3.8.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.8.4  DEEPSLEEP Power Control
      5. 3.8.5  External Memory Interface A (EMIFA)
      6. 3.8.6  DDR2/mDDR Controller
      7. 3.8.7  Serial Peripheral Interface Modules (SPI)
      8. 3.8.8  Programmable Real-Time Unit (PRU)
      9. 3.8.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.8.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.8.11 Boot
      12. 3.8.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.8.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.8.14 Timers
      15. 3.8.15 Multichannel Audio Serial Ports (McASP)
      16. 3.8.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.8.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.8.18 Ethernet Media Access Controller (EMAC)
      19. 3.8.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.8.20 Liquid Crystal Display Controller(LCD)
      21. 3.8.21 Serial ATA Controller (SATA)
      22. 3.8.22 Universal Host-Port Interface (UHPI)
      23. 3.8.23 Universal Parallel Port (uPP)
      24. 3.8.24 Video Port Interface (VPIF)
      25. 3.8.25 General Purpose Input Output
      26. 3.8.26 Reserved and No Connect
      27. 3.8.27 Supply and Ground
    9. 3.9 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. AINTC Hardware Vector Generation
        3. AINTC Hardware Interrupt Nesting Support
        4. AINTC System Interrupt Assignments
        5. AINTC Memory Map
      2. 6.7.2 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. Power Domain States
        2. Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1.  DDR2/mDDR Interface Schematic
        2.  Compatible JEDEC DDR2/mDDR Devices
        3.  PCB Stackup
        4.  Placement
        5.  DDR2/mDDR Keep Out Region
        6.  Bulk Bypass Capacitors
        7.  High-Speed Bypass Capacitors
        8.  Net Classes
        9.  DDR2/mDDR Signal Termination
        10. VREF Routing
        11. DDR2/mDDR CK and ADDR_CTRL Routing
        12. DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
    14. 6.14 Serial ATA Controller (SATA)
      1. 6.14.1 SATA Register Descriptions
      2. 6.14.2 1. SATA Interface
        1. SATA Interface Schematic
        2. Compatible SATA Components and Modes
        3. PCB Stackup Specifications
        4. Routing Specifications
        5. Coupling Capacitors
        6. SATA Interface Clock Source requirements
      3. 6.14.3 SATA Unused Signal Configuration
    15. 6.15 Multichannel Audio Serial Port (McASP)
      1. 6.15.1 McASP Peripheral Registers Description(s)
      2. 6.15.2 McASP Electrical Data/Timing
        1. Multichannel Audio Serial Port 0 (McASP0) Timing
    16. 6.16 Multichannel Buffered Serial Port (McBSP)
      1. 6.16.1 McBSP Peripheral Register Description(s)
      2. 6.16.2 McBSP Electrical Data/Timing
        1. Multichannel Buffered Serial Port (McBSP) Timing
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. Serial Peripheral Interface (SPI) Timing
    18. 6.18 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.18.1 I2C Device-Specific Information
      2. 6.18.2 I2C Peripheral Registers Description(s)
      3. 6.18.3 I2C Electrical Data/Timing
        1. Inter-Integrated Circuit (I2C) Timing
    19. 6.19 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.19.1 UART Peripheral Registers Description(s)
      2. 6.19.2 UART Electrical Data/Timing
    20. 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.20.1 USB0 [USB2.0] Electrical Data/Timing
    21. 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
    22. 6.22 Ethernet Media Access Controller (EMAC)
      1. 6.22.1 EMAC Peripheral Register Description(s)
        1. EMAC Electrical Data/Timing
    23. 6.23 Management Data Input/Output (MDIO)
      1. 6.23.1 MDIO Register Description(s)
      2. 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    24. 6.24 LCD Controller (LCDC)
      1. 6.24.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.24.2 LCD Raster Mode
    25. 6.25 Host-Port Interface (UHPI)
      1. 6.25.1 HPI Device-Specific Information
      2. 6.25.2 HPI Peripheral Register Description(s)
      3. 6.25.3 HPI Electrical Data/Timing
    26. 6.26 Universal Parallel Port (uPP)
      1. 6.26.1 uPP Register Descriptions
      2. 6.26.2 uPP Electrical Data/Timing
    27. 6.27 Video Port Interface (VPIF)
      1. 6.27.1 VPIF Register Descriptions
      2. 6.27.2 VPIF Electrical Data/Timing
    28. 6.28 Enhanced Capture (eCAP) Peripheral
    29. 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.29.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 6.29.2 Trip-Zone Input Timing
    30. 6.30 Timers
      1. 6.30.1 Timer Electrical Data/Timing
    31. 6.31 Real Time Clock (RTC)
      1. 6.31.1 Clock Source
      2. 6.31.2 Real-Time Clock Register Descriptions
    32. 6.32 General-Purpose Input/Output (GPIO)
      1. 6.32.1 GPIO Register Description(s)
      2. 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    33. 6.33 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.33.1 PRUSS Register Descriptions
    34. 6.34 Emulation Logic
      1. 6.34.1 JTAG Port Description
      2. 6.34.2 Scan Chain Configuration Parameters
      3. 6.34.3 Initial Scan Chain Configuration
        1. Adding TAPS to the Scan Chain
      4. 6.34.4 IEEE 1149.1 JTAG
        1. JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
        2. JTAG Test-Port Electrical Data/Timing
      5. 6.34.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCE|361
  • ZWT|361
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview


  • Dual-Core SoC
    • 375- and 456-MHz ARM926EJ-S™ RISC MPU
    • 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
  • ARM926EJ-S Core
    • 32- and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9™ Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2746 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture With Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • Software Support
    • Chip Support Library and DSP Library
  • 128KB of RAM Shared Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM With 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller With one of the Following:
      • 16-Bit DDR2 SDRAM With 256-MB Address Space
      • 16-Bit mDDR SDRAM With 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
  • Serial ATA (SATA) Controller:
    • Supports SATA I (1.5 Gbps) and SATA II
      (3.0 Gbps)
    • Supports All SATA Power-Management Features
    • Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball Pb-Free PBGA [ZWT Suffix],
      0.80-mm Ball Pitch
  • Commercial, Extended, or Industrial Temperature


  • Professional or Private Mobile Radio (PMR)
  • Remote Radio Unit (RRU)
  • Remote Radio Head (RRH)
  • Industrial Automation
  • Currency Inspection
  • Biometric Identification
  • Machine Vision (Low-End)
  • Smart Grid Substation Protection
  • Industrial Portable Navigation Devices


The OMAP-L138 C6000 DSP+ARM processor is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The dual-core architecture of the device provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM9 core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM9 core has separate 16-KB instruction and 16-KB data caches. Both caches are 4-way associative with virtual index virtual tag (VIVT). The ARM9 core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by the ARM9 and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust,” the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects the users’ IP and lets them securely set up the system and begin device operation with known, trusted code.

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but also offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, see the TMS320C674x/OMAP-L1x Processor Security User’s Guide.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The Serial ATA (SATA) controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) provides a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM9 and DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

Device Information(1)

OMAPL138ZCE NFBGA (361) 13,00 mm x 13,00 mm
OMAPL138ZWT NFBGA (361) 16,00 mm x 16,00 mm
For more information on these devices, see Section 8.

Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

OMAP-L138 omap_l138blk_prt586.gif
Note: Not all peripherals are available at the same time due to multiplexing.
Figure 1-1 Functional Block Diagram