SPRS586J June   2009  – January 2017 OMAP-L138

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. 3.4.2.1 ARM Internal Memories
        2. 3.4.2.2 External Memories
        3. 3.4.2.3 DSP Internal Memories
        4. 3.4.2.4 C674x CPU
    5. 3.5 Memory Map Summary
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Pin Multiplexing Control
    8. 3.8 Terminal Functions
      1. 3.8.1  Device Reset, NMI and JTAG
      2. 3.8.2  High-Frequency Oscillator and PLL
      3. 3.8.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.8.4  DEEPSLEEP Power Control
      5. 3.8.5  External Memory Interface A (EMIFA)
      6. 3.8.6  DDR2/mDDR Controller
      7. 3.8.7  Serial Peripheral Interface Modules (SPI)
      8. 3.8.8  Programmable Real-Time Unit (PRU)
      9. 3.8.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.8.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.8.11 Boot
      12. 3.8.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.8.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.8.14 Timers
      15. 3.8.15 Multichannel Audio Serial Ports (McASP)
      16. 3.8.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.8.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.8.18 Ethernet Media Access Controller (EMAC)
      19. 3.8.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.8.20 Liquid Crystal Display Controller(LCD)
      21. 3.8.21 Serial ATA Controller (SATA)
      22. 3.8.22 Universal Host-Port Interface (UHPI)
      23. 3.8.23 Universal Parallel Port (uPP)
      24. 3.8.24 Video Port Interface (VPIF)
      25. 3.8.25 General Purpose Input Output
      26. 3.8.26 Reserved and No Connect
      27. 3.8.27 Supply and Ground
    9. 3.9 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
      2. 6.7.2 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
    14. 6.14 Serial ATA Controller (SATA)
      1. 6.14.1 SATA Register Descriptions
      2. 6.14.2 1. SATA Interface
        1. 6.14.2.1 SATA Interface Schematic
        2. 6.14.2.2 Compatible SATA Components and Modes
        3. 6.14.2.3 PCB Stackup Specifications
        4. 6.14.2.4 Routing Specifications
        5. 6.14.2.5 Coupling Capacitors
        6. 6.14.2.6 SATA Interface Clock Source requirements
      3. 6.14.3 SATA Unused Signal Configuration
    15. 6.15 Multichannel Audio Serial Port (McASP)
      1. 6.15.1 McASP Peripheral Registers Description(s)
      2. 6.15.2 McASP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
    16. 6.16 Multichannel Buffered Serial Port (McBSP)
      1. 6.16.1 McBSP Peripheral Register Description(s)
      2. 6.16.2 McBSP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 6.18 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.18.1 I2C Device-Specific Information
      2. 6.18.2 I2C Peripheral Registers Description(s)
      3. 6.18.3 I2C Electrical Data/Timing
        1. 6.18.3.1 Inter-Integrated Circuit (I2C) Timing
    19. 6.19 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.19.1 UART Peripheral Registers Description(s)
      2. 6.19.2 UART Electrical Data/Timing
    20. 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.20.1 USB0 [USB2.0] Electrical Data/Timing
    21. 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
    22. 6.22 Ethernet Media Access Controller (EMAC)
      1. 6.22.1 EMAC Peripheral Register Description(s)
        1. 6.22.1.1 EMAC Electrical Data/Timing
    23. 6.23 Management Data Input/Output (MDIO)
      1. 6.23.1 MDIO Register Description(s)
      2. 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    24. 6.24 LCD Controller (LCDC)
      1. 6.24.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.24.2 LCD Raster Mode
    25. 6.25 Host-Port Interface (UHPI)
      1. 6.25.1 HPI Device-Specific Information
      2. 6.25.2 HPI Peripheral Register Description(s)
      3. 6.25.3 HPI Electrical Data/Timing
    26. 6.26 Universal Parallel Port (uPP)
      1. 6.26.1 uPP Register Descriptions
      2. 6.26.2 uPP Electrical Data/Timing
    27. 6.27 Video Port Interface (VPIF)
      1. 6.27.1 VPIF Register Descriptions
      2. 6.27.2 VPIF Electrical Data/Timing
    28. 6.28 Enhanced Capture (eCAP) Peripheral
    29. 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.29.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 6.29.2 Trip-Zone Input Timing
    30. 6.30 Timers
      1. 6.30.1 Timer Electrical Data/Timing
    31. 6.31 Real Time Clock (RTC)
      1. 6.31.1 Clock Source
      2. 6.31.2 Real-Time Clock Register Descriptions
    32. 6.32 General-Purpose Input/Output (GPIO)
      1. 6.32.1 GPIO Register Description(s)
      2. 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    33. 6.33 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.33.1 PRUSS Register Descriptions
    34. 6.34 Emulation Logic
      1. 6.34.1 JTAG Port Description
      2. 6.34.2 Scan Chain Configuration Parameters
      3. 6.34.3 Initial Scan Chain Configuration
        1. 6.34.3.1 Adding TAPS to the Scan Chain
      4. 6.34.4 IEEE 1149.1 JTAG
        1. 6.34.4.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
        2. 6.34.4.2 JTAG Test-Port Electrical Data/Timing
      5. 6.34.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCE|361
  • ZWT|361
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Peripheral Information and Electrical Specifications

Parameter Information

Parameter Information Device-Specific Information

OMAP-L138 pm_tstcirc_prs348.gif
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 6-1 Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

Signal Transition Levels

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels.

For 3.3 V I/O, Vref = 1.65 V.

For 1.8 V I/O, Vref = 0.9 V.

For 1.2 V I/O, Vref = 0.6 V.

OMAP-L138 pm_io_volt_prs348.gif Figure 6-2 Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks

OMAP-L138 pm_transvolt_prs348.gif Figure 6-3 Rise and Fall Transition Time Voltage Reference Levels

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.

Power Supplies

Power-On Sequence

The device should be powered-on in the following order:

  1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
  2. Core logic supplies:
    1. All variable 1.3V - 1.0V core logic supplies (CVDD)
    2. All static core logic supplies (RVDD, PLL0_VDDA, PLL1_VDDA, USB_CVDD, SATA_VDD). If voltage scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply and powered up together.
  3. All static 1.8V IO supplies (DVDD18, DDR_DVDD18, USB0_VDDA18, USB1_VDDA18 and SATA_VDDR) and any of the LVCMOS IO supply groups used at 1.8V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).
  4. All analog 3.3V PHY supplies (USB0_VDDA33 and USB1_VDDA33; these are not required if both USB0 and USB1 are not used) and any of the LVCMOS IO supply groups used at 3.3V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).

There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V supplies by more than 2 volts.

RESET must be maintained active until all power supplies have reached their nominal values.

Power-Off Sequence

The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts. There is no specific required voltage ramp down rate for any of the supplies (except as required to meet the above mentioned voltage condition).

Reset

Power-On Reset (POR)

A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence, and RTCK/GP8[0]. If an emulator is driving TCK into the device during reset, then RTCK/GP8[0] will drive out RTCK. If TCK is not being driven into the device during reset, then RTCK/GP8[0] will drive low. RESETOUT in an output for use by other controllers in the system that indicates the device is currently in reset.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and device's emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

RTCK/GP8[0] is maintained active through a POR.

A summary of the effects of Power-On Reset is given below:

  • All internal logic (including emulation logic and the PLL logic) is reset to its default state
  • Internal memory is not maintained through a POR
  • RESETOUT goes active
  • All device pins go to a high-impedance state
  • The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC

CAUTION: A watchdog reset triggers a POR.

Warm Reset

A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low (TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence, and RTCK/GP8[0]. If an emulator is driving TCK into the device during reset, then RTCK/GP8[0] will drive out RTCK. If TCK is not being driven into the device during reset, then RTCK/GP8[0] will drive low. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset.

During an emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available during emulation debug and development.

RTCK/GP8[0] is maintained active through a warm reset.

A summary of the effects of Warm Reset is given below:

  • All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
  • Internal memory is maintained through a warm reset
  • RESETOUT goes active
  • All device pins go to a high-impedance state
  • The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the RTC

Reset Electrical Data Timings

Table 6-1 assumes testing over the recommended operating conditions.

Table 6-1 Reset Timing Requirements ((1), (2))

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tw(RSTL) Pulse width, RESET/TRST low 100 100 100 ns
2 tsu(BPV-RSTH) Setup time, boot pins valid before RESET/TRST high 20 20 20 ns
3 th(RSTH-BPV) Hold time, boot pins valid after RESET/TRST high 20 20 20 ns
4 td(RSTH-RESETOUTH) RESET high to RESETOUT high; Warm reset 4096 4096 4096 cycles(3)
RESET high to RESETOUT high; Power-on Reset 6169 6169 6169
5 td(RSTL-RESETOUTL) Delay time, RESET/TRST low to RESETOUT low 14 16 20 ns
RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-5 for details.
For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this table refer to RESET only (TRST is held high).
OSCIN cycles.
OMAP-L138 td_reset_prs563.gif Figure 6-4 Power-On Reset (RESET and TRST active) Timing
OMAP-L138 td_reset2_prs563.gif Figure 6-5 Warm Reset (RESET active, TRST high) Timing

Crystal Oscillator or External Clock Input

The device includes two choices to provide an external clock input, which is fed to the on-chip PLLs to generate

high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended. Typical load capacitance values are 10-20 pF, where the load capacitance is the series combination of C1 and C2.

The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1, the internal oscillator is disabled.

Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit. Figure 6-7 illustrates the option that uses an external 1.2V clock input.

OMAP-L138 onchip_1-2v_osc_prs483.gif Figure 6-6 On-Chip Oscillator

Table 6-2 Oscillator Timing Requirements

PARAMETER MIN MAX UNIT
fosc Oscillator frequency range (OSCIN/OSCOUT) 12 30 MHz
OMAP-L138 extended_1-2v_clock_prs483.gif Figure 6-7 External 1.2V Clock Source

Table 6-3 OSCIN Timing Requirements for an Externally Driven Clock

PARAMETER MIN MAX UNIT
fOSCIN OSCIN frequency range 12 50 MHz
tc(OSCIN) Cycle time, external clock driven on OSCIN 20 ns
tw(OSCINH) Pulse width high, external clock on OSCIN 0.4 tc(OSCIN) ns
tw(OSCINL) Pulse width low, external clock on OSCIN 0.4 tc(OSCIN) ns
tt(OSCIN) Transition time, OSCIN 0.25P or 10 (1) ns
tj(OSCIN) Period jitter, OSCIN 0.02P ns
Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.

Clock PLLs

The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the DDR2/mDDR Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.

The PLL controller provides the following:

  • Glitch-Free Transitions (on changing clock settings)
  • Domain Clocks Alignment
  • Clock Gating
  • PLL power down

The various clock outputs given by the controller are as follows:

  • Domain Clocks: SYSCLK [1:n]
  • Auxiliary Clock from reference clock source: AUXCLK

Various dividers that can be used are as follows:

  • Post-PLL Divider: POSTDIV
  • SYSCLK Divider: D1, ¼, Dn

Various other controls supported are as follows:

  • PLL Multiplier Control: PLLM
  • Software programmable PLL Bypass: PLLEN

PLL Device-Specific Information

The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8.

OMAP-L138 pll0_filt_prs483.gif Figure 6-8 PLL External Filtering Components

The external filtering components shown above provide noise immunity for the PLLs. PLL0_VDDA and PLL1_VDDA should not be connected together to provide noise immunity between the two PLLs. Likewise, PLL0_VSSA and PLL1_VSSA should not be connected together.

The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology.

The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN = 1.

OMAP-L138 pll_bd_prugj7.gif Figure 6-9 PLL Topology

Table 6-4 Allowed PLL Operating Conditions (PLL0 and PLL1)

NO. PARAMETER Default
Value
MIN MAX UNIT
1 PLLRST: Assertion time during initialization N/A 1000 N/A ns
2 Lock time: The time that the application has to wait for the PLL to acquire lock before setting PLLEN, after changing PREDIV, PLLM, or OSCIN N/A N/A OMAP-L138 eq1_prs483.gif (1) OSCIN
cycles
3 PREDIV: Pre-divider value /1 /1 /32 -
4 PLLREF: PLL input frequency 12 30 (if internal oscillator is used)
50 (if external clock is used)
MHz
5 PLLM: PLL multiplier values x20 x4 x32
6 PLLOUT: PLL output frequency N/A 300 600 MHz
7 POSTDIV: Post-divider value /1 /1 /32 -
The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between300 and 600 MHz, but the frequency going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given voltage operating point.

Device Clock Generation

PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1 manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test points.

PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the DDR2/mDDR Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on the application requirements. In addition, some peripherals have specific clock options independent of the ASYNC clock domain.

Dynamic Voltage and Frequency Scaling (DVFS)

The processor supports multiple operating points by scaling voltage and frequency to minimize power consumption for a given level of processor performance.

Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers (POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values does not require relocking the PLL and provides lower latency to switch between operating points, but at the expense of the frequencies being limited by the integer divide values (only the divide values are altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must relock, incurring additional latency to change between operating points. Detailed information on modifying the PLL Controller settings can be found in the OMAP-L138 C6-Integra DSP+ARM Technical Reference Manual (SPRUH77).

Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching between voltage-frequency operating points, the voltage must always support the desired frequency. When moving from a high-performance operating point to a lower performance operating point, the frequency should be lowered first followed by the voltage. When moving from a low-performance operating point to a higher performance operating point, the voltage should be raised first followed by the frequency. Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained at their nominal voltages at all operating points.

The maximum voltage slew rate for CVdd supply changes is 1 mV/us.

For additional information on power management solutions from TI for this processor, follow the Power Management link in the Product Folder on www.ti.com for this processor.

The processor supports multiple clock domains some of which have clock ratio requirements to each other. SYSCLK1:SYSCLK2:SYSCLK4:SYSCLK6 are synchronous to each other and the SYSCLKn dividers must always be configured such that the ratio between these domains is 1:2:4:1. The ASYNC and ASYNC3 clock domains are asynchronous to the other clock domains and have no specific ratio requirement.

Table 6-5 summarizes the maximum internal clock frequencies at each of the voltage operating points.

Table 6-5 Maximum Internal Clock Frequencies at Each Voltage Operating Point

CLOCK SOURCE CLOCK DOMAIN 1.3V NOM 1.2V NOM 1.1V NOM 1.0V NOM
PLL0_SYSCLK1 DSP subsystem 456 MHz 375 MHz 200 MHz 100 MHz
PLL0_SYSCLK2 SYSCLK2 clock domain peripherals and optional clock source for ASYNC3 clock domain peripherals 228 MHz 187.5 MHz 100 MHz 50 MHz
PLL0_SYSCLK3 Optional clock for ASYNC1 clock domain
(See ASYNC1 row)
PLL0_SYSCLK4 SYSCLK4 domain peripherals 114 MHz 93.75 MHz 50 MHz 25 MHz
PLL0_SYSCLK5 Not used on this processor - - - -
PLL0_SYSCLK6 ARM subsystem 456 MHz 375 MHz 200 MHz 100 MHz
PLL0_SYSCLK7 Optional 50 MHz clock source for EMAC RMII interface 50 MHz 50 MHz - -
PLL1_SYSCLK1 DDR2/mDDR Interface clock source
(memory interface clock is one-half of the value shown)
312 MHz 312 MHz 300 MHz 266 MHz
PLL1_SYSCLK2 Optional clock source for ASYNC3 clock domain peripherals 152 MHz 150 MHz 100 MHz 75 MHz
PLL1_SYSCLK3 Alternate clock source input to PLL Controller 0 75 MHz 75 MHz 75 MHz 75 MHz
McASP AUXCLK Bypass clock source for the McASP 50 MHz 50 MHz 50 MHz 50 MHz
PLL0_AUXCLK Bypass clock source for the USB0 and USB1 48 MHz 48 MHz 48 MHz 48 MHz
ASYNC1 ASYNC Clock Domain (EMIFA) Async Mode 148 MHz 148 MHz 75 MHz 50 MHz
SDRAM Mode 100 MHz 100 MHz 66.6 MHz 50 MHz
ASYNC2 ASYNC2 Clock Domain (multiple peripherals) 50 MHz 50 MHz 50 MHz 50 MHz

Some interfaces have specific limitations on supported modes/speeds at each operating point. See the corresponding peripheral sections of this document for more information.

TI provides software components (called the Power Manager) to perform DVFS and abstract the task from the user. The Power Manager controls changing operating points (both frequency and voltage) and handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions between operating points. The Power Manager is bundled as a component of DSP/BIOS.

Interrupts

The device has a large number of interrupts to service the needs of its many peripherals and subsystems. Both the ARM and C674x CPUs are capable of servicing these interrupts equally. The interrupts can be selectively enabled or disabled in either of the controllers. Also, the ARM and DSP can communicate with each other through interrupts controlled by registers in the SYSCFG module.

ARM CPU Interrupts

The ARM9 CPU core supports two direct interrupts: FIQ and IRQ. The ARM Interrupt Controller (AINTC) extends the number of interrupts to 100, and provides features like programmable masking, priority, hardware nesting support, and interrupt vector generation.

ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy

The ARM Interrupt controller organizes interrupts into the following hierarchy:

  • Peripheral Interrupt Requests
    • Individual Interrupt Sources from Peripherals
  • 101 System Interrupts
    • One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a System Interrupt.
    • After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt
  • 32 Interrupt Channels
    • Each System Interrupt is mapped to one of the 32 Interrupt Channels
    • Channel Number determines the first level of prioritization, Channel 0 is highest priority and 31 lowest.
    • If more than one system interrupt is mapped to a channel, priority within the channel is determined by system interrupt number (0 highest priority)
  • Host Interrupts (FIQ and IRQ)
    • Interrupt Channels 0 and 1 generate the ARM FIQ interrupt
    • Interrupt Channels 2 through 31 Generate the ARM IRQ interrupt
  • Debug Interrupts
    • Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem
    • Sources can be selected from any of the System Interrupts or Host Interrupts

AINTC Hardware Vector Generation

The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system interrupts. The vector is computed in hardware as:

VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE)

Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may dispatched to using a single instruction of type LDR PC, [PC, #-<offset_12>] at the FIQ and IRQ vector locations (0xFFFF0018 and 0xFFFF001C respectively).

AINTC Hardware Interrupt Nesting Support

Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts; only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with the option of automatic nesting on a global or per host interrupt basis; or manual nesting.

AINTC System Interrupt Assignments

Table 6-6 AINTC System Interrupt Assignments

System Interrupt Interrupt Name Source
0 COMMTX ARM
1 COMMRX ARM
2 NINT ARM
3 PRU_EVTOUT0 PRUSS Interrupt
4 PRU_EVTOUT1 PRUSS Interrupt
5 PRU_EVTOUT2 PRUSS Interrupt
6 PRU_EVTOUT3 PRUSS Interrupt
7 PRU_EVTOUT4 PRUSS Interrupt
8 PRU_EVTOUT5 PRUSS Interrupt
9 PRU_EVTOUT6 PRUSS Interrupt
10 PRU_EVTOUT7 PRUSS Interrupt
11 EDMA3_0_CC0_INT0 EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt
12 EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller 0 Error Interrupt
13 EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller 0 Error Interrupt
14 EMIFA_INT EMIFA
15 IIC0_INT I2C0
16 MMCSD0_INT0 MMCSD0 MMC/SD Interrupt
17 MMCSD0_INT1 MMCSD0 SDIO Interrupt
18 PSC0_ALLINT PSC0
19 RTC_IRQS[1:0] RTC
20 SPI0_INT SPI0
21 T64P0_TINT12 Timer64P0 Interrupt 12
22 T64P0_TINT34 Timer64P0 Interrupt 34
23 T64P1_TINT12 Timer64P1 Interrupt 12
24 T64P1_TINT34 Timer64P1 Interrupt 34
25 UART0_INT UART0
26 - Reserved
27 MPU_BOOTCFG_ERR Shared MPU and SYSCFG Address/Protection Error Interrupt
28 SYSCFG_CHIPINT0 SYSCFG CHIPSIG Register
29 SYSCFG_CHIPINT1 SYSCFG CHIPSIG Register
30 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register
31 SYSCFG_CHIPINT3 SYSCFG CHIPSIG Register
32 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Error Interrupt
33 EMAC_C0RXTHRESH EMAC - Core 0 Receive Threshold Interrupt
34 EMAC_C0RX EMAC - Core 0 Receive Interrupt
35 EMAC_C0TX EMAC - Core 0 Transmit Interrupt
36 EMAC_C0MISC EMAC - Core 0 Miscellaneous Interrupt
37 EMAC_C1RXTHRESH EMAC - Core 1 Receive Threshold Interrupt
38 EMAC_C1RX EMAC - Core 1 Receive Interrupt
39 EMAC_C1TX EMAC - Core 1 Transmit Interrupt
40 EMAC_C1MISC EMAC - Core 1 Miscellaneous Interrupt
41 DDR2_MEMERR DDR2 Controller
42 GPIO_B0INT GPIO Bank 0 Interrupt
43 GPIO_B1INT GPIO Bank 1 Interrupt
44 GPIO_B2INT GPIO Bank 2 Interrupt
45 GPIO_B3INT GPIO Bank 3 Interrupt
46 GPIO_B4INT GPIO Bank 4 Interrupt
47 GPIO_B5INT GPIO Bank 5 Interrupt
48 GPIO_B6INT GPIO Bank 6 Interrupt
49 GPIO_B7INT GPIO Bank 7 Interrupt
50 GPIO_B8INT GPIO Bank 8 Interrupt
51 IIC1_INT I2C1
52 LCDC_INT LCD Controller
53 UART_INT1 UART1
54 MCASP_INT McASP0 Combined RX / TX Interrupts
55 PSC1_ALLINT PSC1
56 SPI1_INT SPI1
57 UHPI_ARMINT UHPI ARM Interrupt
58 USB0_INT USB0 Interrupt
59 USB1_HCINT USB1 OHCI Host Controller Interrupt
60 USB1_RWAKEUP USB1 Remote Wakeup Interrupt
61 UART2_INT UART2
62 - Reserved
63 EHRPWM0 HiResTimer / PWM0 Interrupt
64 EHRPWM0TZ HiResTimer / PWM0 Trip Zone Interrupt
65 EHRPWM1 HiResTimer / PWM1 Interrupt
66 EHRPWM1TZ HiResTimer / PWM1 Trip Zone Interrupt
67 SATA_INT SATA Controller
68 T64P2_ALL Timer64P2 - Combined TINT12 and TINT34
69 ECAP0 ECAP0
70 ECAP1 ECAP1
71 ECAP2 ECAP2
72 MMCSD1_INT0 MMCSD1 MMC/SD Interrupt
73 MMCSD1_INT1 MMCSD1 SDIO Interrupt
74 T64P2_CMPINT0 Timer64P2 - Compare 0
75 T64P2_CMPINT1 Timer64P2 - Compare 1
76 T64P2_CMPINT2 Timer64P2 - Compare 2
77 T64P2_CMPINT3 Timer64P2 - Compare 3
78 T64P2_CMPINT4 Timer64P2 - Compare 4
79 T64P2_CMPINT5 Timer64P2 - Compare 5
80 T64P2_CMPINT6 Timer64P2 - Compare 6
81 T64P2_CMPINT7 Timer64P2 - Compare 7
82 T64P3_CMPINT0 Timer64P3 - Compare 0
83 T64P3_CMPINT1 Timer64P3 - Compare 1
84 T64P3_CMPINT2 Timer64P3 - Compare 2
85 T64P3_CMPINT3 Timer64P3 - Compare 3
86 T64P3_CMPINT4 Timer64P3 - Compare 4
87 T64P3_CMPINT5 Timer64P3 - Compare 5
88 T64P3_CMPINT6 Timer64P3 - Compare 6
89 T64P3_CMPINT7 Timer64P3 - Compare 7
90 ARMCLKSTOPREQ PSC0
91 uPP_ALLINT uPP Combined Interrupt
  • Channel I End-of-Line Interrupt
  • Channel I End-of-Window Interrupt
  • Channel I DMA Access Interrupt
  • Channel I Overflow-Underrun Interrupt
  • Channel I DMA Programming Error Interrupt
  • Channel Q End-of-Line Interrupt
  • Channel Q End-of-Window Interrupt
  • Channel Q DMA Access Interrupt
  • Channel Q Overflow-Underrun Interrupt
  • Channel Q DMA Programming Error Interrupt
92 VPIF_ALLINT VPIF Combined Interrupt
  • Channel 0 Frame Interrupt
  • Channel 1 Frame Interrupt
  • Channel 2 Frame Interrupt
  • Channel 3 Frame Interrupt
  • Error Interrupt
93 EDMA3_1_CC0_INT0 EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt
94 EDMA3_1_CC0_ERRINT EDMA3_1Channel Controller 0 Error Interrupt
95 EDMA3_1_TC0_ERRINT EDMA3_1 Transfer Controller 0 Error Interrupt
96 T64P3_ALL Timer64P 3 - Combined TINT12 and TINT34
97 MCBSP0_RINT McBSP0 Receive Interrupt
98 MCBSP0_XINT McBSP0 Transmit Interrupt
99 MCBSP1_RINT McBSP1 Receive Interrupt
100 MCBSP1_XINT McBSP1 Transmit Interrupt

AINTC Memory Map

Table 6-7 AINTC Memory Map

BYTE ADDRESS ACRONYM DESCRIPTION
0xFFFE E000 REV Revision Register
0xFFFE E004 CR Control Register
0xFFFE E008 - 0xFFFE E00F - Reserved
0xFFFE E010 GER Global Enable Register
0xFFFE E014 - 0xFFFE E01B - Reserved
0xFFFE E01C GNLR Global Nesting Level Register
0xFFFE E020 SISR System Interrupt Status Indexed Set Register
0xFFFE E024 SICR System Interrupt Status Indexed Clear Register
0xFFFE E028 EISR System Interrupt Enable Indexed Set Register
0xFFFE E02C EICR System Interrupt Enable Indexed Clear Register
0xFFFE E030 - Reserved
0xFFFE E034 HIEISR Host Interrupt Enable Indexed Set Register
0xFFFE E038 HIEICR Host Interrupt Enable Indexed Clear Register
0xFFFE E03C - 0xFFFE E04F - Reserved
0xFFFE E050 VBR Vector Base Register
0xFFFE E054 VSR Vector Size Register
0xFFFE E058 VNR Vector Null Register
0xFFFE E05C - 0xFFFE E07F - Reserved
0xFFFE E080 GPIR Global Prioritized Index Register
0xFFFE E084 GPVR Global Prioritized Vector Register
0xFFFE E088 - 0xFFFE E1FF - Reserved
0xFFFE E200 SRSR[1] System Interrupt Status Raw / Set Registers
0xFFFE E204 SRSR[2]
0xFFFE E208 SRSR[3]
0xFFFE E20C SRSR[4]
0xFFFE E210- 0xFFFE E27F - Reserved
0xFFFE E280 SECR[1] System Interrupt Status Enabled / Clear Registers
0xFFFE E284 SECR[2]
0xFFFE E288 SECR[3]
0xFFFE E28C SECR[4]
0xFFFE E290 - 0xFFFE E2FF - Reserved
0xFFFE E300 ESR[1] System Interrupt Enable Set Registers
0xFFFE E304 ESR[2]
0xFFFE E308 ESR[3]
0xFFFE E30C ESR[4]
0xFFFE E310 - 0xFFFE E37F - Reserved
0xFFFE E380 ECR[1] System Interrupt Enable Clear Registers
0xFFFE E384 ECR[2]
0xFFFE E388 ECR[3]
0xFFFE E38C ECR[4]
0xFFFE E390 - 0xFFFE E3FF - Reserved
0xFFFE E400 - 0xFFFE E45B CMR[0] Channel Map Registers
0xFFFE E404 CMR[1]
0xFFFE E408 CMR[2]
0xFFFE E40C CMR[3]
0xFFFE E410 CMR[4]
0xFFFE E414 CMR[5]
0xFFFE E418 CMR[6]
0xFFFE E41C CMR[7]
0xFFFE E420 CMR[8]
0xFFFE E424 CMR[9]
0xFFFE E428 CMR[10]
0xFFFE E42C CMR[11]
0xFFFE E430 CMR[12]
0xFFFE E434 CMR[13]
0xFFFE E438 CMR[14]
0xFFFE E43C CMR[15]
0xFFFE E440 CMR[16]
0xFFFE E444 CMR[17]
0xFFFE E448 CMR[18]
0xFFFE E44C CMR[19]
0xFFFE E450 CMR[20]
0xFFFE E454 CMR[21]
0xFFFE E458 CMR[22]
0xFFFE E45C CMR[23]
0xFFFE E460 CMR[24]
0xFFFE E464 CMR[25]
0xFFFE E468 - 0xFFFE E8FF - Reserved
0xFFFE E900 HIPIR[1] Host Interrupt Prioritized Index Registers
0xFFFE E904 HIPIR[2]
0xFFFE E908 - 0xFFFE F0FF - Reserved
0xFFFE F100 HINLR[1] Host Interrupt Nesting Level Registers
0xFFFE F104 HINLR[2]
0xFFFE F108 - 0xFFFE F4FF - Reserved
0xFFFE F500 HIER Host Interrupt Enable Register
0xFFFE F504 - 0xFFFE F5FF - Reserved
0xFFFE F600 HIPVR[1] Host Interrupt Prioritized Vector Registers
0xFFFE F604 HIPVR[2]
0xFFFE F608 - 0xFFFE FFFF - Reserved

DSP Interrupts

The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-8. Also, the interrupt controller controls the generation of the CPU exceptions, NMI, and emulation interrupts. Table 6-9 summarizes the C674x interrupt controller registers and memory locations.

Refer to the C674x DSP MegaModule Reference Guide (SPRUFK5) and the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for details of the C674x interrupts.

Table 6-8 OMAP-L138 DSP Interrupts

EVT# Interrupt Name Source
0 EVT0 C674x Int Ctl 0
1 EVT1 C674x Int Ctl 1
2 EVT2 C674x Int Ctl 2
3 EVT3 C674x Int Ctl 3
4 T64P0_TINT12 Timer64P0 - TINT12
5 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register
6 PRU_EVTOUT0 PRUSS Interrupt
7 EHRPWM0 HiResTimer/PWM0 Interrupt
8 EDMA3_0_CC0_INT1 EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
9 EMU_DTDMA C674x-ECM
10 EHRPWM0TZ HiResTimer/PWM0 Trip Zone Interrupt
11 EMU_RTDXRX C674x-RTDX
12 EMU_RTDXTX C674x-RTDX
13 IDMAINT0 C674x-EMC
14 IDMAINT1 C674x-EMC
15 MMCSD0_INT0 MMCSD0 MMC/SD Interrupt
16 MMCSD0_INT1 MMCSD0 SDIO Interrupt
17 PRU_EVTOUT1 PRUSS Interrupt
18 EHRPWM1 HiResTimer/PWM1 Interrupt
19 USB0_INT USB0 Interrupt
20 USB1_HCINT USB1 OHCI Host Controller Interrupt
21 USB1_RWAKEUP USB1 Remote Wakeup Interrupt
22 PRU_EVTOUT2 PRUSS Interrupt
23 EHRPWM1TZ HiResTimer/PWM1 Trip Zone Interrupt
24 SATA_INT SATA Controller
25 T64P2_TINTALL Timer64P2 Combined TINT12 and TINT 34 Interrupt
26 EMAC_C0RXTHRESH EMAC - Core 0 Receive Threshold Interrupt
27 EMAC_C0RX EMAC - Core 0 Receive Interrupt
28 EMAC_C0TX EMAC - Core 0 Transmit Interrupt
29 EMAC_C0MISC EMAC - Core 0 Miscellaneous Interrupt
30 EMAC_C1RXTHRESH EMAC - Core 1 Receive Threshold Interrupt
31 EMAC_C1RX EMAC - Core 1 Receive Interrupt
32 EMAC_C1TX EMAC - Core 1 Transmit Interrupt
33 EMAC_C1MISC EMAC - Core 1 Miscellaneous Interrupt
34 UHPI_DSPINT UHPI DSP Interrupt
35 PRU_EVTOUT3 PRUSS Interrupt
36 IIC0_INT I2C0
37 SP0_INT SPI0
38 UART0_INT UART0
39 PRU_EVTOUT5 PRUSS Interrupt
40 T64P1_TINT12 Timer64P1 Interrupt 12
41 GPIO_B1INT GPIO Bank 1 Interrupt
42 IIC1_INT I2C1
43 SPI1_INT SPI1
44 PRU_EVTOUT6 PRUSS Interrupt
45 ECAP0 ECAP0
46 UART_INT1 UART1
47 ECAP1 ECAP1
48 T64P1_TINT34 Timer64P1 Interrupt 34
49 GPIO_B2INT GPIO Bank 2 Interrupt
50 PRU_EVTOUT7 PRUSS Interrupt
51 ECAP2 ECAP2
52 GPIO_B3INT GPIO Bank 3 Interrupt
53 MMCSD1_INT1 MMCSD1 SDIO Interrupt
54 GPIO_B4INT GPIO Bank 4 Interrupt
55 EMIFA_INT EMIFA
56 EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller 0 Error Interrupt
57 EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller 0 Error Interrupt
58 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Error Interrupt
59 GPIO_B5INT GPIO Bank 5 Interrupt
60 DDR2_MEMERR DDR2 Memory Error Interrupt
61 MCASP0_INT McASP0 Combined RX/TX Interrupts
62 GPIO_B6INT GPIO Bank 6 Interrupt
63 RTC_IRQS RTC Combined
64 T64P0_TINT34 Timer64P0 Interrupt 34
65 GPIO_B0INT GPIO Bank 0 Interrupt
66 PRU_EVTOUT4 PRUSS Interrupt
67 SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register
68 MMCSD1_INT0 MMCSD1 MMC/SD Interrupt
69 UART2_INT UART2
70 PSC0_ALLINT PSC0
71 PSC1_ALLINT PSC1
72 GPIO_B7INT GPIO Bank 7 Interrupt
73 LCDC_INT LDC Controller
74 PROTERR SYSCFG Protection Shared Interrupt
75 GPIO_B8INT GPIO Bank 8 Interrupt
76 - 77 - Reserved
78  T64P2_CMPINT0 Timer64P2 - Compare Interrupt 0
79  T64P2_CMPINT1 Timer64P2 - Compare Interrupt 1
80  T64P2_CMPINT2 Timer64P2 - Compare Interrupt 2
81  T64P2_CMPINT3 Timer64P2 - Compare Interrupt 3
82  T64P2_CMPINT4 Timer64P2 - Compare Interrupt 4
83  T64P2_CMPINT5 Timer64P2 - Compare Interrupt 5
84  T64P2_CMPINT6 Timer64P2 - Compare Interrupt 6
85  T64P2_CMPINT7 Timer64P2 - Compare Interrupt 7
86 T64P3_TINTALL Timer64P3 Combined TINT12 and TINT 34 Interrupt
87 MCBSP0_RINT McBSP0 Receive Interrupt
88 MCBSP0_XINT McBSP0 Transmit Interrupt
89 MCBSP1_RINT McBSP1 Receive Interrupt
90 MCBSP1_XINT McBSP1 Transmit Interrupt
91 EDMA3_1_CC0_INT1 EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
92 EDMA3_1_CC0_ERRINT EDMA3_1 Channel Controller 0 Error Interrupt
93 EDMA3_1_TC0_ERRINT EDMA3_1 Transfer Controller 0 Error Interrupt
94 UPP_INT uPP Combined Interrupt
95 VPIF_INT VPIF Combined Interrupt
96 INTERR C674x-Int Ctl
97 EMC_IDMAERR C674x-EMC
98 - 112 - Reserved
113 PMC_ED C674x-PMC
114 - 115 - Reserved
116 UMC_ED1 C674x-UMC
117 UMC_ED2 C674x-UMC
118 PDC_INT C674x-PDC
119 SYS_CMPA C674x-SYS
120 PMC_CMPA C674x-PMC
121 PMC_CMPA C674x-PMC
122 DMC_CMPA C674x-DMC
123 DMC_CMPA C674x-DMC
124 UMC_CMPA C674x-UMC
125 UMC_CMPA C674x-UMC
126 EMC_CMPA C674x-EMC
127 EMC_BUSERR C674x-EMC

Table 6-9 C674x DSP Interrupt Controller Registers

BYTE ADDRESS ACRONYM DESCRIPTION
0x0180 0000 EVTFLAG0 Event flag register 0
0x0180 0004 EVTFLAG1 Event flag register 1
0x0180 0008 EVTFLAG2 Event flag register 2
0x0180 000C EVTFLAG3 Event flag register 3
0x0180 0020 EVTSET0 Event set register 0
0x0180 0024 EVTSET1 Event set register 1
0x0180 0028 EVTSET2 Event set register 2
0x0180 002C EVTSET3 Event set register 3
0x0180 0040 EVTCLR0 Event clear register 0
0x0180 0044 EVTCLR1 Event clear register 1
0x0180 0048 EVTCLR2 Event clear register 2
0x0180 004C EVTCLR3 Event clear register 3
0x0180 0080 EVTMASK0 Event mask register 0
0x0180 0084 EVTMASK1 Event mask register 1
0x0180 0088 EVTMASK2 Event mask register 2
0x0180 008C EVTMASK3 Event mask register 3
0x0180 00A0 MEVTFLAG0 Masked event flag register 0
0x0180 00A4 MEVTFLAG1 Masked event flag register 1
0x0180 00A8 MEVTFLAG2 Masked event flag register 2
0x0180 00AC MEVTFLAG3 Masked event flag register 3
0x0180 00C0 EXPMASK0 Exception mask register 0
0x0180 00C4 EXPMASK1 Exception mask register 1
0x0180 00C8 EXPMASK2 Exception mask register 2
0x0180 00CC EXPMASK3 Exception mask register 3
0x0180 00E0 MEXPFLAG0 Masked exception flag register 0
0x0180 00E4 MEXPFLAG1 Masked exception flag register 1
0x0180 00E8 MEXPFLAG2 Masked exception flag register 2
0x0180 00EC MEXPFLAG3 Masked exception flag register 3
0x0180 0104 INTMUX1 Interrupt mux register 1
0x0180 0108 INTMUX2 Interrupt mux register 2
0x0180 010C INTMUX3 Interrupt mux register 3
0x0180 0140 - 0x0180 0144 - Reserved
0x0180 0180 INTXSTAT Interrupt exception status
0x0180 0184 INTXCLR Interrupt exception clear
0x0180 0188 INTDMASK Dropped interrupt mask register
0x0180 01C0 EVTASRT Event assert register

Power and Sleep Controller (PSC)

The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off, clock on/off, resets (device level and module level). It is used primarily to provide granular power control for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and provides clock and reset control.

The PSC includes the following features:

  • Provides a software interface to:
    • Control module clock enable/disable
    • Control module reset
    • Control CPU local reset
  • Supports IcePick emulation features: power, clock and reset
  • PSC0 controls 16 local PSCs.

    PSC1 controls 32 local PSCs.

Table 6-10 Power and Sleep Controller (PSC) Registers

PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C1 0000 0x01E2 7000 REVID Peripheral Revision and Class Information Register
0x01C1 0018 0x01E2 7018 INTEVAL Interrupt Evaluation Register
0x01C1 0040 0x01E2 7040 MERRPR0 Module Error Pending Register 0 (module 0-15) (PSC0)
Module Error Pending Register 0 (module 0-31) (PSC1)
0x01C1 0050 0x01E2 7050 MERRCR0 Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
0x01C1 0060 0x01E2 7060 PERRPR Power Error Pending Register
0x01C1 0068 0x01E2 7068 PERRCR Power Error Clear Register
0x01C1 0120 0x01E2 7120 PTCMD Power Domain Transition Command Register
0x01C1 0128 0x01E2 7128 PTSTAT Power Domain Transition Status Register
0x01C1 0200 0x01E2 7200 PDSTAT0 Power Domain 0 Status Register
0x01C1 0204 0x01E2 7204 PDSTAT1 Power Domain 1 Status Register
0x01C1 0300 0x01E2 7300 PDCTL0 Power Domain 0 Control Register
0x01C1 0304 0x01E2 7304 PDCTL1 Power Domain 1 Control Register
0x01C1 0400 0x01E2 7400 PDCFG0 Power Domain 0 Configuration Register
0x01C1 0404 0x01E2 7404 PDCFG1 Power Domain 1 Configuration Register
0x01C1 0800 0x01E2 7800 MDSTAT0 Module 0 Status Register
0x01C1 0804 0x01E2 7804 MDSTAT1 Module 1 Status Register
0x01C1 0808 0x01E2 7808 MDSTAT2 Module 2 Status Register
0x01C1 080C 0x01E2 780C MDSTAT3 Module 3 Status Register
0x01C1 0810 0x01E2 7810 MDSTAT4 Module 4 Status Register
0x01C1 0814 0x01E2 7814 MDSTAT5 Module 5 Status Register
0x01C1 0818 0x01E2 7818 MDSTAT6 Module 6 Status Register
0x01C1 081C 0x01E2 781C MDSTAT7 Module 7 Status Register
0x01C1 0820 0x01E2 7820 MDSTAT8 Module 8 Status Register
0x01C1 0824 0x01E2 7824 MDSTAT9 Module 9 Status Register
0x01C1 0828 0x01E2 7828 MDSTAT10 Module 10 Status Register
0x01C1 082C 0x01E2 782C MDSTAT11 Module 11 Status Register
0x01C1 0830 0x01E2 7830 MDSTAT12 Module 12 Status Register
0x01C1 0834 0x01E2 7834 MDSTAT13 Module 13 Status Register
0x01C1 0838 0x01E2 7838 MDSTAT14 Module 14 Status Register
0x01C1 083C 0x01E2 783C MDSTAT15 Module 15 Status Register
- 0x01E2 7840 MDSTAT16 Module 16 Status Register
- 0x01E2 7844 MDSTAT17 Module 17 Status Register
- 0x01E2 7848 MDSTAT18 Module 18 Status Register
- 0x01E2 784C MDSTAT19 Module 19 Status Register
- 0x01E2 7850 MDSTAT20 Module 20 Status Register
- 0x01E2 7854 MDSTAT21 Module 21 Status Register
- 0x01E2 7858 MDSTAT22 Module 22 Status Register
- 0x01E2 785C MDSTAT23 Module 23 Status Register
- 0x01E2 7860 MDSTAT24 Module 24 Status Register
- 0x01E2 7864 MDSTAT25 Module 25 Status Register
- 0x01E2 7868 MDSTAT26 Module 26 Status Register
- 0x01E2 786C MDSTAT27 Module 27 Status Register
- 0x01E2 7870 MDSTAT28 Module 28 Status Register
- 0x01E2 7874 MDSTAT29 Module 29 Status Register
- 0x01E2 7878 MDSTAT30 Module 30 Status Register
- 0x01E2 787C MDSTAT31 Module 31 Status Register
0x01C1 0A00 0x01E2 7A00 MDCTL0 Module 0 Control Register
0x01C1 0A04 0x01E2 7A04 MDCTL1 Module 1 Control Register
0x01C1 0A08 0x01E2 7A08 MDCTL2 Module 2 Control Register
0x01C1 0A0C 0x01E2 7A0C MDCTL3 Module 3 Control Register
0x01C1 0A10 0x01E2 7A10 MDCTL4 Module 4 Control Register
0x01C1 0A14 0x01E2 7A14 MDCTL5 Module 5 Control Register
0x01C1 0A18 0x01E2 7A18 MDCTL6 Module 6 Control Register
0x01C1 0A1C 0x01E2 7A1C MDCTL7 Module 7 Control Register
0x01C1 0A20 0x01E2 7A20 MDCTL8 Module 8 Control Register
0x01C1 0A24 0x01E2 7A24 MDCTL9 Module 9 Control Register
0x01C1 0A28 0x01E2 7A28 MDCTL10 Module 10 Control Register
0x01C1 0A2C 0x01E2 7A2C MDCTL11 Module 11 Control Register
0x01C1 0A30 0x01E2 7A30 MDCTL12 Module 12 Control Register
0x01C1 0A34 0x01E2 7A34 MDCTL13 Module 13 Control Register
0x01C1 0A38 0x01E2 7A38 MDCTL14 Module 14 Control Register
0x01C1 0A3C 0x01E2 7A3C MDCTL15 Module 15 Control Register
- 0x01E2 7A40 MDCTL16 Module 16 Control Register
- 0x01E2 7A44 MDCTL17 Module 17 Control Register
- 0x01E2 7A48 MDCTL18 Module 18 Control Register
- 0x01E2 7A4C MDCTL19 Module 19 Control Register
- 0x01E2 7A50 MDCTL20 Module 20 Control Register
- 0x01E2 7A54 MDCTL21 Module 21 Control Register
- 0x01E2 7A58 MDCTL22 Module 22 Control Register
- 0x01E2 7A5C MDCTL23 Module 23 Control Register
- 0x01E2 7A60 MDCTL24 Module 24 Control Register
- 0x01E2 7A64 MDCTL25 Module 25 Control Register
- 0x01E2 7A68 MDCTL26 Module 26 Control Register
- 0x01E2 7A6C MDCTL27 Module 27 Control Register
- 0x01E2 7A70 MDCTL28 Module 28 Control Register
- 0x01E2 7A74 MDCTL29 Module 29 Control Register
- 0x01E2 7A78 MDCTL30 Module 30 Control Register
- 0x01E2 7A7C MDCTL31 Module 31 Control Register

Power Domain and Module Topology

The device includes two PSC modules.

Each PSC module controls clock states for several of the on chip modules, controllers and interconnect components. Table 6-11 and Table 6-12 lists the set of peripherals/modules that are controlled by the PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset) module states. The module states and terminology are defined in Section 6.8.1.2.

Table 6-11 PSC0 Default Module Configuration

LPSC
Number
Module Name Power Domain Default Module State Auto Sleep/Wake Only
0 EDMA3 Channel Controller 0 AlwaysON (PD0) SwRstDisable
1 EDMA3 Transfer Controller 0 AlwaysON (PD0) SwRstDisable
2 EDMA3 Transfer Controller 1 AlwaysON (PD0) SwRstDisable
3 EMIFA (Br7) AlwaysON (PD0) SwRstDisable
4 SPI 0 AlwaysON (PD0) SwRstDisable
5 MMC/SD 0 AlwaysON (PD0) SwRstDisable
6 ARM Interrupt Controller AlwaysON (PD0) SwRstDisable
7 ARM RAM/ROM AlwaysON (PD0) Enable Yes
8
9 UART 0 AlwaysON (PD0) SwRstDisable
10 SCR0 (Br 0, Br 1, Br 2, Br 8) AlwaysON (PD0) Enable Yes
11 SCR1 (Br 4) AlwaysON (PD0) Enable Yes
12 SCR2 (Br 3, Br 5, Br 6) AlwaysON (PD0) Enable Yes
13 PRUSS AlwaysON (PD0) SwRstDisable
14 ARM AlwaysON (PD0) SwRstDisable
15 DSP PD_DSP (PD1) Enable

Table 6-12 PSC1 Default Module Configuration

LPSC
Number
Module Name Power Domain Default Module State Auto Sleep/Wake Only
0 EDMA3 Channel Controller 1 AlwaysON (PD0) SwRstDisable
1 USB0 (USB2.0) AlwaysON (PD0) SwRstDisable
2 USB1 (USB1.1) AlwaysON (PD0) SwRstDisable
3 GPIO AlwaysON (PD0) SwRstDisable
4 UHPI AlwaysON (PD0) SwRstDisable
5 EMAC AlwaysON (PD0) SwRstDisable
6 DDR2 (and SCR_F3) AlwaysON (PD0) SwRstDisable
7 McASP0 ( + McASP0 FIFO) AlwaysON (PD0) SwRstDisable
8 SATA AlwaysON (PD0) SwRstDisable
9 VPIF AlwaysON (PD0) SwRstDisable
10 SPI 1 AlwaysON (PD0) SwRstDisable
11 I2C 1 AlwaysON (PD0) SwRstDisable
12 UART 1 AlwaysON (PD0) SwRstDisable
13 UART 2 AlwaysON (PD0) SwRstDisable
14 McBSP0 ( + McBSP0 FIFO) AlwaysON (PD0) SwRstDisable
15 McBSP1 ( + McBSP1 FIFO) AlwaysON (PD0) SwRstDisable
16 LCDC AlwaysON (PD0) SwRstDisable
17 eHRPWM0/1 AlwaysON (PD0) SwRstDisable
18 MMCSD1 AlwaysON (PD0) SwRstDisable
19 uPP AlwaysON (PD0) SwRstDisable
20 ECAP0/1/2 AlwaysON (PD0) SwRstDisable
21 EDMA3 Transfer Controller 2 AlwaysON (PD0) SwRstDisable
22
23
24 SCR_F0 (and bridge F0) AlwaysON (PD0) Enable Yes
25 SCR_F1 (and bridge F1) AlwaysON (PD0) Enable Yes
26 SCR_F2 (and bridge F2) AlwaysON (PD0) Enable Yes
27 SCR_F6 (and bridge F3) AlwaysON (PD0) Enable Yes
28 SCR_F7 (and bridge F4) AlwaysON (PD0) Enable Yes
29 SCR_F8 (and bridge F5) AlwaysON (PD0) Enable Yes
30 Bridge F7 (DDR Controller path) AlwaysON (PD0) Enable Yes
31 Shared RAM (including SCR_F4 and bridge F6) PD_SHRAM Enable

Power Domain States

A power domain can only be in one of the two states: ON or OFF, defined as follows:

  • ON: power to the domain is on
  • OFF: power to the domain is off

For both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the ON state when the chip is powered-on. This domain is not programmable to OFF state.

  • On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
  • On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128K Shared RAM

Module States

The PSC defines several possible states for a module. This states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are defined in Table 6-13.

Table 6-13 Module States

Module State Module Reset Module Clock Module State Definition
Enable De-asserted On A module in the enable state has its module reset de-asserted and it has its clock on. This is the normal operational state for a given module
Disable De-asserted Off A module in the disabled state has its module reset de-asserted and it has its module clock off. This state is typically used for disabling a module clock to save power. The device is designed in full static CMOS, so when you stop a module clock, it retains the module’s state. When the clock is restarted, the module resumes operating from the stopping point.
SyncReset Asserted On A module state in the SyncReset state has its module reset asserted and it has its clock on. Generally, software is not expected to initiate this state
SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted and it has its clock disabled. After initial power-on, several modules come up in the SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep De-asserted Off A module in the Auto Sleep state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it can “automatically” transition to “Enable” state whenever there is an internal read/write request made to it, and after servicing the request it will “automatically” transition into the sleep state (with module reset re de-asserted and module clock disabled), without any software intervention. The transition from sleep to enabled and back to sleep state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data.
Auto Wake De-asserted Off A module in the Auto Wake state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it will “automatically” transition to “Enable” state whenever there is an internal read/write request made to it, and will remain in the “Enabled” state from then on (with module reset re de-asserted and module clock on), without any software intervention. The transition from sleep to enabled state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data.

Enhanced Direct Memory Access Controller (EDMA3)

The EDMA3 controller handles all data transfers between memories and the device slave peripherals on the device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses.

EDMA3 Channel Synchronization Events

Each EDMA3 channel controller supports up to 32 channels which service peripherals and memory. Table 6-14 lists the source of the EDMA3 synchronization events associated with each of the programmable EDMA channels.

Table 6-14 EDMA Synchronization Events

EDMA3 Channel Controller 0
Event Event Name / Source Event Event Name / Source
0 McASP0 Receive 16 MMCSD0 Receive
1 McASP0 Transmit 17 MMCSD0 Transmit
2 McBSP0 Receive 18 SPI1 Receive
3 McBSP0 Transmit 19 SPI1 Transmit
4 McBSP1 Receive 20 PRU_EVTOUT6
5 McBSP1 Transmit 21 PRU_EVTOUT7
6 GPIO Bank 0 Interrupt 22 GPIO Bank 2 Interrupt
7 GPIO Bank 1 Interrupt 23 GPIO Bank 3 Interrupt
8 UART0 Receive 24 I2C0 Receive
9 UART0 Transmit 25 I2C0 Transmit
10 Timer64P0 Event Out 12 26 I2C1 Receive
11 Timer64P0 Event Out 34 27 I2C1 Transmit
12 UART1 Receive 28 GPIO Bank 4 Interrupt
13 UART1 Transmit 29 GPIO Bank 5 Interrupt
14 SPI0 Receive 30 UART2 Receive
15 SPI0 Transmit 31 UART2 Transmit
EDMA3 Channel Controller 1
Event Event Name / Source Event Event Name / Source
0 Timer64P2 Compare Event 0 16 GPIO Bank 6 Interrupt
1 Timer64P2 Compare Event 1 17 GPIO Bank 7 Interrupt
2 Timer64P2 Compare Event 2 18 GPIO Bank 8 Interrupt
3 Timer64P2 Compare Event 3 19 Reserved
4 Timer64P2 Compare Event 4 20 Reserved
5 Timer64P2 Compare Event 5 21 Reserved
6 Timer64P2 Compare Event 6 22 Reserved
7 Timer64P2 Compare Event 7 23 Reserved
8 Timer64P3 Compare Event 0 24 Timer64P2 Event Out 12
9 Timer64P3 Compare Event 1 25 Timer64P2 Event Out 34
10 Timer64P3 Compare Event 2 26 Timer64P3 Event Out 12
11 Timer64P3 Compare Event 3 27 Timer64P3 Event Out 34
12 Timer64P3 Compare Event 4 28 MMCSD1 Receive
13 Timer64P3 Compare Event 5 29 MMCSD1 Transmit
14 Timer64P3 Compare Event 6 30 Reserved
15 Timer64P3 Compare Event 7 31 Reserved

EDMA3 Peripheral Register Descriptions

Table 6-15 is the list of EDMA3 Channel Controller Registers and Table 6-16 is the list of EDMA3 Transfer Controller registers.

Table 6-15 EDMA3 Channel Controller (EDMA3CC) Registers

EDMA3_0 Channel
Controller 0
BYTE ADDRESS
EDMA3_1 Channel
Controller 0
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01C0 0000 0x01E3 0000 PID Peripheral Identification Register
0x01C0 0004 0x01E3 0004 CCCFG EDMA3CC Configuration Register
Global Registers
0x01C0 0200 0x01E3 0200 QCHMAP0 QDMA Channel 0 Mapping Register
0x01C0 0204 0x01E3 0204 QCHMAP1 QDMA Channel 1 Mapping Register
0x01C0 0208 0x01E3 0208 QCHMAP2 QDMA Channel 2 Mapping Register
0x01C0 020C 0x01E3 020C QCHMAP3 QDMA Channel 3 Mapping Register
0x01C0 0210 0x01E3 0210 QCHMAP4 QDMA Channel 4 Mapping Register
0x01C0 0214 0x01E3 0214 QCHMAP5 QDMA Channel 5 Mapping Register
0x01C0 0218 0x01E3 0218 QCHMAP6 QDMA Channel 6 Mapping Register
0x01C0 021C 0x01E3 021C QCHMAP7 QDMA Channel 7 Mapping Register
0x01C0 0240 0x01E3 0240 DMAQNUM0 DMA Channel Queue Number Register 0
0x01C0 0244 0x01E3 0244 DMAQNUM1 DMA Channel Queue Number Register 1
0x01C0 0248 0x01E3 0248 DMAQNUM2 DMA Channel Queue Number Register 2
0x01C0 024C 0x01E3 024C DMAQNUM3 DMA Channel Queue Number Register 3
0x01C0 0260 0x01E3 0260 QDMAQNUM QDMA Channel Queue Number Register
0x01C0 0284 0x01E3 0284 QUEPRI Queue Priority Register(1)
0x01C0 0300 0x01E3 0300 EMR Event Missed Register
0x01C0 0308 0x01E3 0308 EMCR Event Missed Clear Register
0x01C0 0310 0x01E3 0310 QEMR QDMA Event Missed Register
0x01C0 0314 0x01E3 0314 QEMCR QDMA Event Missed Clear Register
0x01C0 0318 0x01E3 0318 CCERR EDMA3CC Error Register
0x01C0 031C 0x01E3 031C CCERRCLR EDMA3CC Error Clear Register
0x01C0 0320 0x01E3 0320 EEVAL Error Evaluate Register
0x01C0 0340 0x01E3 0340 DRAE0 DMA Region Access Enable Register for Region 0
0x01C0 0348 0x01E3 0348 DRAE1 DMA Region Access Enable Register for Region 1
0x01C0 0350 0x01E3 0350 DRAE2 DMA Region Access Enable Register for Region 2
0x01C0 0358 0x01E3 0358 DRAE3 DMA Region Access Enable Register for Region 3
0x01C0 0380 0x01E3 0380 QRAE0 QDMA Region Access Enable Register for Region 0
0x01C0 0384 0x01E3 0384 QRAE1 QDMA Region Access Enable Register for Region 1
0x01C0 0388 0x01E3 0388 QRAE2 QDMA Region Access Enable Register for Region 2
0x01C0 038C 0x01E3 038C QRAE3 QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043C 0x01E3 0400 - 0x01E3 043C Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C 0x01E3 0440 - 0x01E3 047C Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600 0x01E3 0600 QSTAT0 Queue 0 Status Register
0x01C0 0604 0x01E3 0604 QSTAT1 Queue 1 Status Register
0x01C0 0620 0x01E3 0620 QWMTHRA Queue Watermark Threshold A Register
0x01C0 0640 0x01E3 0640 CCSTAT EDMA3CC Status Register
Global Channel Registers
0x01C0 1000 0x01E3 1000 ER Event Register
0x01C0 1008 0x01E3 1008 ECR Event Clear Register
0x01C0 1010 0x01E3 1010 ESR Event Set Register
0x01C0 1018 0x01E3 1018 CER Chained Event Register
0x01C0 1020 0x01E3 1020 EER Event Enable Register
0x01C0 1028 0x01E3 1028 EECR Event Enable Clear Register
0x01C0 1030 0x01E3 1030 EESR Event Enable Set Register
0x01C0 1038 0x01E3 1038 SER Secondary Event Register
0x01C0 1040 0x01E3 1040 SECR Secondary Event Clear Register
0x01C0 1050 0x01E3 1050 IER Interrupt Enable Register
0x01C0 1058 0x01E3 1058 IECR Interrupt Enable Clear Register
0x01C0 1060 0x01E3 1060 IESR Interrupt Enable Set Register
0x01C0 1068 0x01E3 1068 IPR Interrupt Pending Register
0x01C0 1070 0x01E3 1070 ICR Interrupt Clear Register
0x01C0 1078 0x01E3 1078 IEVAL Interrupt Evaluate Register
0x01C0 1080 0x01E3 1080 QER QDMA Event Register
0x01C0 1084 0x01E3 1084 QEER QDMA Event Enable Register
0x01C0 1088 0x01E3 1088 QEECR QDMA Event Enable Clear Register
0x01C0 108C 0x01E3 108C QEESR QDMA Event Enable Set Register
0x01C0 1090 0x01E3 1090 QSER QDMA Secondary Event Register
0x01C0 1094 0x01E3 1094 QSECR QDMA Secondary Event Clear Register
Shadow Region 0 Channel Registers
0x01C0 2000 0x01E3 2000 ER Event Register
0x01C0 2008 0x01E3 2008 ECR Event Clear Register
0x01C0 2010 0x01E3 2010 ESR Event Set Register
0x01C0 2018 0x01E3 2018 CER Chained Event Register
0x01C0 2020 0x01E3 2020 EER Event Enable Register
0x01C0 2028 0x01E3 2028 EECR Event Enable Clear Register
0x01C0 2030 0x01E3 2030 EESR Event Enable Set Register
0x01C0 2038 0x01E3 2038 SER Secondary Event Register
0x01C0 2040 0x01E3 2040 SECR Secondary Event Clear Register
0x01C0 2050 0x01E3 2050 IER Interrupt Enable Register
0x01C0 2058 0x01E3 2058 IECR Interrupt Enable Clear Register
0x01C0 2060 0x01E3 2060 IESR Interrupt Enable Set Register
0x01C0 2068 0x01E3 2068 IPR Interrupt Pending Register
0x01C0 2070 0x01E3 2070 ICR Interrupt Clear Register
0x01C0 2078 0x01E3 2078 IEVAL Interrupt Evaluate Register
0x01C0 2080 0x01E3 2080 QER QDMA Event Register
0x01C0 2084 0x01E3 2084 QEER QDMA Event Enable Register
0x01C0 2088 0x01E3 2088 QEECR QDMA Event Enable Clear Register
0x01C0 208C 0x01E3 208C QEESR QDMA Event Enable Set Register
0x01C0 2090 0x01E3 2090 QSER QDMA Secondary Event Register
0x01C0 2094 0x01E3 2094 QSECR QDMA Secondary Event Clear Register
Shadow Region 1 Channel Registers
0x01C0 2200 0x01E3 2200 ER Event Register
0x01C0 2208 0x01E3 2208 ECR Event Clear Register
0x01C0 2210 0x01E3 2210 ESR Event Set Register
0x01C0 2218 0x01E3 2218 CER Chained Event Register
0x01C0 2220 0x01E3 2220 EER Event Enable Register
0x01C0 2228 0x01E3 2228 EECR Event Enable Clear Register
0x01C0 2230 0x01E3 2230 EESR Event Enable Set Register
0x01C0 2238 0x01E3 2238 SER Secondary Event Register
0x01C0 2240 0x01E3 2240 SECR Secondary Event Clear Register
0x01C0 2250 0x01E3 2250 IER Interrupt Enable Register
0x01C0 2258 0x01E3 2258 IECR Interrupt Enable Clear Register
0x01C0 2260 0x01E3 2260 IESR Interrupt Enable Set Register
0x01C0 2268 0x01E3 2268 IPR Interrupt Pending Register
0x01C0 2270 0x01E3 2270 ICR Interrupt Clear Register
0x01C0 2278 0x01E3 2278 IEVAL Interrupt Evaluate Register
0x01C0 2280 0x01E3 2280 QER QDMA Event Register
0x01C0 2284 0x01E3 2284 QEER QDMA Event Enable Register
0x01C0 2288 0x01E3 2288 QEECR QDMA Event Enable Clear Register
0x01C0 228C 0x01E3 228C QEESR QDMA Event Enable Set Register
0x01C0 2290 0x01E3 2290 QSER QDMA Secondary Event Register
0x01C0 2294 0x01E3 2294 QSECR QDMA Secondary Event Clear Register
0x01C0 4000 - 0x01C0 4FFF 0x01E3 4000 - 0x01E3 4FFF Parameter RAM (PaRAM)
On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.

Table 6-16 EDMA3 Transfer Controller (EDMA3TC) Registers

EDMA3_0
Transfer Controller 0
BYTE ADDRESS
EDMA3_0
Transfer Controller 1
BYTE ADDRESS
EDMA3_1
Transfer Controller 0
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01C0 8000 0x01C0 8400 0x01E3 8000 PID Peripheral Identification Register
0x01C0 8004 0x01C0 8404 0x01E3 8004 TCCFG EDMA3TC Configuration Register
0x01C0 8100 0x01C0 8500 0x01E3 8100 TCSTAT EDMA3TC Channel Status Register
0x01C0 8120 0x01C0 8520 0x01E3 8120 ERRSTAT Error Status Register
0x01C0 8124 0x01C0 8524 0x01E3 8124 ERREN Error Enable Register
0x01C0 8128 0x01C0 8528 0x01E3 8128 ERRCLR Error Clear Register
0x01C0 812C 0x01C0 852C 0x01E3 812C ERRDET Error Details Register
0x01C0 8130 0x01C0 8530 0x01E3 8130 ERRCMD Error Interrupt Command Register
0x01C0 8140 0x01C0 8540 0x01E3 8140 RDRATE Read Command Rate Register
0x01C0 8240 0x01C0 8640 0x01E3 8240 SAOPT Source Active Options Register
0x01C0 8244 0x01C0 8644 0x01E3 8244 SASRC Source Active Source Address Register
0x01C0 8248 0x01C0 8648 0x01E3 8248 SACNT Source Active Count Register
0x01C0 824C 0x01C0 864C 0x01E3 824C SADST Source Active Destination Address Register
0x01C0 8250 0x01C0 8650 0x01E3 8250 SABIDX Source Active B-Index Register
0x01C0 8254 0x01C0 8654 0x01E3 8254 SAMPPRXY Source Active Memory Protection Proxy Register
0x01C0 8258 0x01C0 8658 0x01E3 8258 SACNTRLD Source Active Count Reload Register
0x01C0 825C 0x01C0 865C 0x01E3 825C SASRCBREF Source Active Source Address B-Reference Register
0x01C0 8260 0x01C0 8660 0x01E3 8260 SADSTBREF Source Active Destination Address B-Reference Register
0x01C0 8280 0x01C0 8680 0x01E3 8280 DFCNTRLD Destination FIFO Set Count Reload Register
0x01C0 8284 0x01C0 8684 0x01E3 8284 DFSRCBREF Destination FIFO Set Source Address B-Reference Register
0x01C0 8288 0x01C0 8688 0x01E3 8288 DFDSTBREF Destination FIFO Set Destination Address B-Reference Register
0x01C0 8300 0x01C0 8700 0x01E3 8300 DFOPT0 Destination FIFO Options Register 0
0x01C0 8304 0x01C0 8704 0x01E3 8304 DFSRC0 Destination FIFO Source Address Register 0
0x01C0 8308 0x01C0 8708 0x01E3 8308 DFCNT0 Destination FIFO Count Register 0
0x01C0 830C 0x01C0 870C 0x01E3 830C DFDST0 Destination FIFO Destination Address Register 0
0x01C0 8310 0x01C0 8710 0x01E3 8310 DFBIDX0 Destination FIFO B-Index Register 0
0x01C0 8314 0x01C0 8714 0x01E3 8314 DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0
0x01C0 8340 0x01C0 8740 0x01E3 8340 DFOPT1 Destination FIFO Options Register 1
0x01C0 8344 0x01C0 8744 0x01E3 8344 DFSRC1 Destination FIFO Source Address Register 1
0x01C0 8348 0x01C0 8748 0x01E3 8348 DFCNT1 Destination FIFO Count Register 1
0x01C0 834C 0x01C0 874C 0x01E3 834C DFDST1 Destination FIFO Destination Address Register 1
0x01C0 8350 0x01C0 8750 0x01E3 8350 DFBIDX1 Destination FIFO B-Index Register 1
0x01C0 8354 0x01C0 8754 0x01E3 8354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1
0x01C0 8380 0x01C0 8780 0x01E3 8380 DFOPT2 Destination FIFO Options Register 2
0x01C0 8384 0x01C0 8784 0x01E3 8384 DFSRC2 Destination FIFO Source Address Register 2
0x01C0 8388 0x01C0 8788 0x01E3 8388 DFCNT2 Destination FIFO Count Register 2
0x01C0 838C 0x01C0 878C 0x01E3 838C DFDST2 Destination FIFO Destination Address Register 2
0x01C0 8390 0x01C0 8790 0x01E3 8390 DFBIDX2 Destination FIFO B-Index Register 2
0x01C0 8394 0x01C0 8794 0x01E3 8394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2
0x01C0 83C0 0x01C0 87C0 0x01E3 83C0 DFOPT3 Destination FIFO Options Register 3
0x01C0 83C4 0x01C0 87C4 0x01E3 83C4 DFSRC3 Destination FIFO Source Address Register 3
0x01C0 83C8 0x01C0 87C8 0x01E3 83C8 DFCNT3 Destination FIFO Count Register 3
0x01C0 83CC 0x01C0 87CC 0x01E3 83CC DFDST3 Destination FIFO Destination Address Register 3
0x01C0 83D0 0x01C0 87D0 0x01E3 83D0 DFBIDX3 Destination FIFO B-Index Register 3
0x01C0 83D4 0x01C0 87D4 0x01E3 83D4 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3

Table 6-17 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA3 events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-18 shows the parameter set entry registers with relative memory address locations within each of the parameter sets.

Table 6-17 EDMA3 Parameter Set RAM

EDMA3_0
Channel Controller 0
BYTE ADDRESS RANGE
EDMA3_1
Channel Controller 0
BYTE ADDRESS RANGE
DESCRIPTION
0x01C0 4000 - 0x01C0 401F 0x01E3 4000 - 0x01E3 401F Parameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403F 0x01E3 4020 - 0x01E3 403F Parameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01CC0 405F 0x01E3 4040 - 0x01CE3 405F Parameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407F 0x01E3 4060 - 0x01E3 407F Parameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409F 0x01E3 4080 - 0x01E3 409F Parameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BF 0x01E3 40A0 - 0x01E3 40BF Parameters Set 5 (8 32-bit words)
... ... ...
0x01C0 4FC0 - 0x01C0 4FDF 0x01E3 4FC0 - 0x01E3 4FDF Parameters Set 126 (8 32-bit words)
0x01C0 4FE0 - 0x01C0 4FFF 0x01E3 4FE0 - 0x01E3 4FFF Parameters Set 127 (8 32-bit words)

Table 6-18 Parameter Set Entries

OFFSET BYTE ADDRESS
WITHIN THE PARAMETER SET
ACRONYM PARAMETER ENTRY
0x0000 OPT Option
0x0004 SRC Source Address
0x0008 A_B_CNT A Count, B Count
0x000C DST Destination Address
0x0010 SRC_DST_BIDX Source B Index, Destination B Index
0x0014 LINK_BCNTRLD Link Address, B Count Reload
0x0018 SRC_DST_CIDX Source C Index, Destination C Index
0x001C CCNT C Count

External Memory Interface A (EMIFA)

EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However on this device, EMIFA also provides a secondary interface to SDRAM.

EMIFA Asynchronous Memory Support

EMIFA supports asynchronous:

  • SRAM memories
  • NAND Flash memories
  • NOR Flash memories

The EMIFA data bus width is up to 16-bits.The device supports up to 23 address lines and two external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2]).

Each chip select has the following individually programmable attributes:

  • Data Bus Width
  • Read cycle timings: setup, hold, strobe
  • Write cycle timings: setup, hold, strobe
  • Bus turn around time
  • Extended Wait Option With Programmable Timeout
  • Select Strobe Option
  • NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.

EMIFA Synchronous DRAM Memory Support

The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are:

  • One, Two, and Four Bank SDRAM devices
  • Devices with Eight, Nine, Ten, and Eleven Column Address
  • CAS Latency of two or three clock cycles
  • Sixteen Bit Data Bus Width

Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory contents; since the SDRAM will continue to refresh itself even without clocks from the device. Powerdown mode achieves even lower power, except the device must periodically wake the SDRAM up and issue refreshes if data retention is required.

Finally, note that the EMIFA does not support Mobile SDRAM devices.

Table 6-19 shows the supported SDRAM configurations for EMIFA.

Table 6-19 EMIFA Supported SDRAM Configurations(1)

SDRAM Memory Data Bus Width (bits) Number of Memories EMIFA Data Bus Size (bits) Rows Columns Banks Total Memory (Mbits) Total Memory (Mbytes) Memory Density (Mbits)
1 16 16 8 1 256 32 256
1 16 16 8 2 512 64 512
1 16 16 8 4 1024 128 1024
1 16 16 9 1 512 64 512
1 16 16 9 2 1024 128 1024
16 1 16 16 9 4 2048 256 2048
1 16 16 10 1 1024 128 1024
1 16 16 10 2 2048 256 2048
1 16 16 10 4 4096 512 4096
1 16 16 11 1 2048 256 2048
1 16 16 11 2 4096 512 4096
1 16 15 11 4 4096 512 4096
2 16 16 8 1 256 32 128
2 16 16 8 2 512 64 256
2 16 16 8 4 1024 128 512
2 16 16 9 1 512 64 256
2 16 16 9 2 1024 128 512
8 2 16 16 9 4 2048 256 1024
2 16 16 10 1 1024 128 512
2 16 16 10 2 2048 256 1024
2 16 16 10 4 4096 512 2048
2 16 16 11 1 2048 256 1024
2 16 16 11 2 4096 512 2048
2 16 15 11 4 4096 512 2048
The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of supporting these densities are not available in the market.

EMIFA SDRAM Loading Limitations

EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by board simulation using IBIS models.

EMIFA Connection Examples

Figure 6-10 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to EMIFA simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].

The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects, but this must be supported by second stage boot code stored in the external flash.

A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-11. This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to bootload it.

OMAP-L138 dg_emif_3flash_prs483.gif Figure 6-10 Connection Diagram: SDRAM, NOR, NAND
OMAP-L138 dg_emif_flash_prs483.gif Figure 6-11 EMIFA Connection Diagram: Multiple NAND Flash Planes

External Memory Interface Register Descriptions

Table 6-20 External Memory Interface (EMIFA) Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x6800 0000 MIDR Module ID Register
0x6800 0004 AWCC Asynchronous Wait Cycle Configuration Register
0x6800 0008 SDCR SDRAM Configuration Register
0x6800 000C SDRCR SDRAM Refresh Control Register
0x6800 0010 CE2CFG Asynchronous 1 Configuration Register
0x6800 0014 CE3CFG Asynchronous 2 Configuration Register
0x6800 0018 CE4CFG Asynchronous 3 Configuration Register
0x6800 001C CE5CFG Asynchronous 4 Configuration Register
0x6800 0020 SDTIMR SDRAM Timing Register
0x6800 003C SDSRETR SDRAM Self Refresh Exit Timing Register
0x6800 0040 INTRAW EMIFA Interrupt Raw Register
0x6800 0044 INTMSK EMIFA Interrupt Mask Register
0x6800 0048 INTMSKSET EMIFA Interrupt Mask Set Register
0x6800 004C INTMSKCLR EMIFA Interrupt Mask Clear Register
0x6800 0060 NANDFCR NAND Flash Control Register
0x6800 0064 NANDFSR NAND Flash Status Register
0x6800 0070 NANDF1ECC NAND Flash 1 ECC Register (CS2 Space)
0x6800 0074 NANDF2ECC NAND Flash 2 ECC Register (CS3 Space)
0x6800 0078 NANDF3ECC NAND Flash 3 ECC Register (CS4 Space)
0x6800 007C NANDF4ECC NAND Flash 4 ECC Register (CS5 Space)
0x6800 00BC NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register
0x6800 00C0 NAND4BITECC1 NAND Flash 4-Bit ECC Register 1
0x6800 00C4 NAND4BITECC2 NAND Flash 4-Bit ECC Register 2
0x6800 00C8 NAND4BITECC3 NAND Flash 4-Bit ECC Register 3
0x6800 00CC NAND4BITECC4 NAND Flash 4-Bit ECC Register 4
0x6800 00D0 NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 1
0x6800 00D4 NANDERRADD2 NAND Flash 4-Bit ECC Error Address Register 2
0x6800 00D8 NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1
0x6800 00DC NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2

EMIFA Electrical Data/Timing

Table 6-21 through Table 6-24 assume testing over recommended operating conditions.

Table 6-21 Timing Requirements for EMIFA SDRAM Interface

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
19 tsu(EMA_DV-EM_CLKH) Input setup time, read data valid on EMA_D[15:0] before EMA_CLK rising 2 3 3 ns
20 th(CLKH-DIV) Input hold time, read data valid on EMA_D[15:0] after EMA_CLK rising 1.6 1.6 1.6 ns

Table 6-22 Switching Characteristics for EMIFA SDRAM Interface

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tc(CLK) Cycle time, EMIF clock EMA_CLK 10 15 20 ns
2 tw(CLK) Pulse width, EMIF clock EMA_CLK high or low 3 5 8 ns
3 td(CLKH-CSV) Delay time, EMA_CLK rising to EMA_CS[0] valid 7 9.5 13 ns
4 toh(CLKH-CSIV) Output hold time, EMA_CLK rising to EMA_CS[0] invalid 1 1 1 ns
5 td(CLKH-DQMV) Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid 7 9.5 13 ns
6 toh(CLKH-DQMIV) Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid 1 1 1 ns
7 td(CLKH-AV) Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] valid 7 9.5 13 ns
8 toh(CLKH-AIV) Output hold time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] invalid 1 1 1 ns
9 td(CLKH-DV) Delay time, EMA_CLK rising to EMA_D[15:0] valid 7 9.5 13 ns
10 toh(CLKH-DIV) Output hold time, EMA_CLK rising to EMA_D[15:0] invalid 1 1 1 ns
11 td(CLKH-RASV) Delay time, EMA_CLK rising to EMA_RAS valid 7 9.5 13 ns
12 toh(CLKH-RASIV) Output hold time, EMA_CLK rising to EMA_RAS invalid 1 1 1 ns
13 td(CLKH-CASV) Delay time, EMA_CLK rising to EMA_CAS valid 7 9.5 13 ns
14 toh(CLKH-CASIV) Output hold time, EMA_CLK rising to EMA_CAS invalid 1 1 1 ns
15 td(CLKH-WEV) Delay time, EMA_CLK rising to EMA_WE valid 7 9.5 13 ns
16 toh(CLKH-WEIV) Output hold time, EMA_CLK rising to EMA_WE invalid 1 1 1 ns
17 tdis(CLKH-DHZ) Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated 7 9.5 13 ns
18 tena(CLKH-DLZ) Output hold time, EMA_CLK rising to EMA_D[15:0] driving 1 1 1 ns
OMAP-L138 emif1_prs254.gif Figure 6-12 EMIFA Basic SDRAM Write Operation
OMAP-L138 emif2_3_8_prs254.gif Figure 6-13 EMIFA Basic SDRAM Read Operation

Table 6-23 Timing Requirements for EMIFA Asynchronous Memory Interface (1)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
READS and WRITES
E tc(CLK) Cycle time, EMIFA module clock 6.75 13.33 20 ns
2 tw(EM_WAIT) Pulse duration, EM_WAIT assertion and deassertion 2E 2E 2E ns
READS
12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 3 5 7 ns
13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 0 0 0 ns
14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase(2) 4E+3 4E+3 4E+3 ns
WRITES
28 tsu (EMWEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase(2) 4E+3 4E+3 4E+3 ns
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns
Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 6-24 Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3)

NO. PARAMETER 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN Nom MAX
READS and WRITES
1 td(TURNAROUND) Turn around time (TA)*E - 3 (TA)*E (TA)*E + 3 ns
READS
3 tc(EMRCYCLE) EMIF read cycle time (EW = 0) (RS+RST+RH)*E - 3 (RS+RST+RH)*E (RS+RST+RH)*E + 3 ns
EMIF read cycle time (EW = 1) (RS+RST+RH+EWC)*E - 3 (RS+RST+RH+EWC)*E (RS+RST+RH+EWC)*E + 3 ns
4 tsu(EMCEL-EMOEL) Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0) (RS)*E-3 (RS)*E (RS)*E+3 ns
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1) -3 0 +3 ns
5 th(EMOEH-EMCEH) Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0) (RH)*E - 3 (RH)*E (RH)*E + 3 ns
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1) -3 0 +3 ns
6 tsu(EMBAV-EMOEL) Output setup time, EMA_BA[1:0] valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns
7 th(EMOEH-EMBAIV) Output hold time, EMA_OE high to EMA_BA[1:0] invalid (RH)*E-3 (RH)*E (RH)*E+3 ns
8 tsu(EMBAV-EMOEL) Output setup time, EMA_A[13:0] valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns
9 th(EMOEH-EMAIV) Output hold time, EMA_OE high to EMA_A[13:0] invalid (RH)*E-3 (RH)*E (RH)*E+3 ns
10 tw(EMOEL) EMA_OE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns
EMA_OE active low width (EW = 1) (RST+EWC)*E-3 (RST+EWC)*E (RST+EWC)*E+3 ns
11 td(EMWAITH-EMOEH) Delay time from EMA_WAIT deasserted to EMA_OE high 3E-3 4E 4E+3 ns
28 tsu(EMARW-EMOEL) Output setup time, EMA_A_RW valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns
29 th(EMOEH-EMARW) Output hold time, EMA_OE high to EMA_A_RW invalid (RH)*E-3 (RH)*E (RH)*E+3 ns
WRITES
15 tc(EMWCYCLE) EMIF write cycle time (EW = 0) (WS+WST+WH)*E-3 (WS+WST+WH)*E (WS+WST+WH)*E+3 ns
EMIF write cycle time (EW = 1) (WS+WST+WH+EWC)*E - 3 (WS+WST+WH+EWC)*E (WS+WST+WH+EWC)*E + 3 ns
16 tsu(EMCEL-EMWEL) Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0) (WS)*E - 3 (WS)*E (WS)*E + 3 ns
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1) -3 0 +3 ns
17 th(EMWEH-EMCEH) Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0) (WH)*E-3 (WH)*E (WH)*E+3 ns
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1) -3 0 +3 ns
18 tsu(EMDQMV-EMWEL) Output setup time, EMA_BA[1:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns
19 th(EMWEH-EMDQMIV) Output hold time, EMA_WE high to EMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
20 tsu(EMBAV-EMWEL) Output setup time, EMA_BA[1:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns
21 th(EMWEH-EMBAIV) Output hold time, EMA_WE high to EMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
22 tsu(EMAV-EMWEL) Output setup time, EMA_A[13:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns
23 th(EMWEH-EMAIV) Output hold time, EMA_WE high to EMA_A[13:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
24 tw(EMWEL) EMA_WE active low width (EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns
EMA_WE active low width (EW = 1) (WST+EWC)*E-3 (WST+EWC)*E (WST+EWC)*E+3 ns
25 td(EMWAITH-EMWEH) Delay time from EMA_WAIT deasserted to EMA_WE high 3E-3 4E 4E+3 ns
26 tsu(EMDV-EMWEL) Output setup time, EMA_D[15:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns
27 th(EMWEH-EMDIV) Output hold time, EMA_WE high to EMA_D[15:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
30 tsu(EMARW-EMWEL) Output setup time, EMA_A_RW valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns
31 th(EMWEH-EMARW) Output hold time, EMA_WE high to EMA_A_RW invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns.
EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
OMAP-L138 td_async_rd_prs586.gif Figure 6-14 Asynchronous Memory Read Timing for EMIFA
OMAP-L138 td_async_wrt_prs586.gif Figure 6-15 Asynchronous Memory Write Timing for EMIFA
OMAP-L138 td_async_wrd1_prs586.gif Figure 6-16 EMA_WAIT Read Timing Requirements
OMAP-L138 td_async_wwt_prs586.gif Figure 6-17 EMA_WAIT Write Timing Requirements

DDR2/mDDR Memory Controller

The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.

The DDR2/mDDR Memory Controller support the following features:

  • JESD79-2A standard compliant DDR2 SDRAM
  • Mobile DDR SDRAM
  • 256 MByte memory space for DDR2
  • 256 MByte memory space for mDDR
  • CAS latencies:
    • DDR2: 2, 3, 4 and 5
    • mDDR: 2 and 3
  • Internal banks:
    • DDR2: 1, 2, 4 and 8
    • mDDR:1, 2 and 4
  • Burst length: 8
  • Burst type: sequential
  • 1 chip select (CS) signal
  • Page sizes: 256, 512, 1024, and 2048
  • SDRAM autoinitialization
  • Self-refresh mode
  • Partial array self-refresh (for mDDR)
  • Power down mode
  • Prioritized refresh
  • Programmable refresh rate and backlog counter
  • Programmable timing parameters
  • Little endian

DDR2/mDDR Memory Controller Electrical Data/Timing

Table 6-25 Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR Memory Controller

No. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tc(DDR_CLK) Cycle time,
DDR_CLKP / DDR_CLKN
DDR2 125 156 125 150 (1) (1) MHz
mDDR 105 150 100 133 95 133
DDR2 is not supported at this voltage operating point.

DDR2/mDDR Memory Controller Register Description(s)

Table 6-26 DDR2/mDDR Memory Controller Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0xB000 0000 REVID Revision ID Register
0xB000 0004 SDRSTAT SDRAM Status Register
0xB000 0008 SDCR SDRAM Configuration Register
0xB000 000C SDRCR SDRAM Refresh Control Register
0xB000 0010 SDTIMR1 SDRAM Timing Register 1
0xB000 0014 SDTIMR2 SDRAM Timing Register 2
0xB000 001C SDCR2 SDRAM Configuration Register 2
0xB000 0020 PBBPR Peripheral Bus Burst Priority Register
0xB000 0040 PC1 Performance Counter 1 Registers
0xB000 0044 PC2 Performance Counter 2 Register
0xB000 0048 PCC Performance Counter Configuration Register
0xB000 004C PCMRS Performance Counter Master Region Select Register
0xB000 0050 PCT Performance Counter Time Register
0xB000 00C0 IRR Interrupt Raw Register
0xB000 00C4 IMR Interrupt Mask Register
0xB000 00C8 IMSR Interrupt Mask Set Register
0xB000 00CC IMCR Interrupt Mask Clear Register
0xB000 00E4 DRPYC1R DDR PHY Control Register 1
0x01E2 C000 VTPIO_CTL VTP IO Control Register

DDR2/mDDR Interface

This section provides the timing specification for the DDR2/mDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).

DDR2/mDDR Interface Schematic

Figure 6-18 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The dual-memory system shown in Figure 6-19. Pin numbers for the device can be obtained from the pin description section.

OMAP-L138 f_1_praarupdated3.gif
See Figure 6-25 for DQGATE routing specifications.
For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR, these capacitors can be eliminated completely.
VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.
Figure 6-18 DDR2/mDDR Single-Memory High Level Schematic
OMAP-L138 f_2_updatedpraar3.gif
See Figure 6-25 for DQGATE routing specifications.
For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR, these capacitors can be eliminated completely.
VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.
Figure 6-19 DDR2/mDDR Dual-Memory High Level Schematic

Compatible JEDEC DDR2/mDDR Devices

Table 6-27 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2-400/mDDR-200 speed grade DDR2/mDDR devices.

The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control signals are shared just like regular dual chip memory configurations.

Table 6-27 Compatible JEDEC DDR2/mDDR Devices

NO. PARAMETER MIN MAX UNIT
1 JEDEC DDR2/mDDR Device Speed Grade(1) DDR2-400/mDDR-200
2 JEDEC DDR2/mDDR Device Bit Width x8 x16 Bits
3 JEDEC DDR2/mDDR Device Count(2) 1 2 Devices
Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.
Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories

PCB Stackup

The minimum stackup required for routing the device is a six layer stack as shown in Table 6-28. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.Complete stack up specifications are provided in Table 6-29.

Table 6-28 Device Minimum PCB Stack Up

LAYER TYPE DESCRIPTION
1 Signal Top Routing Mostly Horizontal
2 Plane Ground
3 Plane Power
4 Signal Internal Routing
5 Plane Ground
6 Signal Bottom Routing Mostly Vertical

Table 6-29 PCB Stack Up Specifications

NO. PARAMETER MIN TYP MAX UNIT
1 PCB Routing/Plane Layers 6
2 Signal Routing Layers 3
3 Full ground layers under DDR2/mDDR routing region 2
4 Number of ground plane cuts allowed within DDR routing region 0
5 Number of ground reference planes required for each DDR2/mDDR routing layer 1
6 Number of layers between DDR2/mDDR routing layer and reference ground plane 0
7 PCB Routing Feature Size 4 Mils
8 PCB Trace Width w 4 Mils
8 PCB BGA escape via pad size 18 Mils
9 PCB BGA escape via hole size 8 Mils
10 Device BGA pad size(1)
11 DDR2/mDDR Device BGA pad size(2)
12 Single Ended Impedance, Zo 50 75 Ω
13 Impedance Control(3) Z-5 Z Z+5 Ω
Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.
Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.
Z is the nominal singled ended impedance selected for the PCB specified by item 12.

Placement

Figure 6-19 shows the required placement for the device as well as the DDR2/mDDR devices. The dimensions for Figure 6-20 are defined in Table 6-30. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR device is omitted from the placement.

OMAP-L138 f2_praar3.gif Figure 6-20 OMAP-L138 and DDR2/mDDR Device Placement

Table 6-30 Placement Specifications(1)(2)

NO. PARAMETER MIN MAX UNIT
1 X 1750 Mils
2 Y 1280 Mils
3 Y Offset (3) 650 Mils
4 Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region(4) 4 w(5)
See Figure 6-20 for dimension definitions.
Measurements from center of device to center of DDR2/mDDR device.
For single memory systems it is recommended that Y Offset be as small as possible.
Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by a ground plane.
w = PCB trace width as defined in Table 6-29.

DDR2/mDDR Keep Out Region

The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-21. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-30.

OMAP-L138 f3_praar3.gif Figure 6-21 DDR2/mDDR Keepout Region

Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other circuitry. Table 6-31 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the Soc and DDR2/mDDR interfaces. Additional bulk bypass capacitance may be needed for other circuitry.

Table 6-31 Bulk Bypass Capacitors

NO. PARAMETER MIN MAX UNIT
1 DDR_DVDD18 Supply Bulk Bypass Capacitor Count(1) 3 Devices
2 DDR_DVDD18 Supply Bulk Bypass Total Capacitance 30 μF
3 DDR#1 Bulk Bypass Capacitor Count(1) 1 Devices
4 DDR#1 Bulk Bypass Total Capacitance 22 μF
5 DDR#2 Bulk Bypass Capacitor Count(1)(2) 1 Devices
6 DDR#2 Bulk Bypass Total Capacitance(2) 22 μF
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps.
Only used on dual-memory systems.

High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, Soc/DDR2/mDDR power, and Soc/DDR2/mDDR ground connections. Table 6-32 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB.

Table 6-32 High-Speed Bypass Capacitors

NO. PARAMETER MIN MAX UNIT
1 HS Bypass Capacitor Package Size(1) 0402 10 Mils
2 Distance from HS bypass capacitor to device being bypassed 250 Mils
3 Number of connection vias for each HS bypass capacitor 2(4) Vias
4 Trace length from bypass capacitor contact to connection via 1 30 Mils
5 Number of connection vias for each DDR2/mDDR device power or ground balls 1 Vias
6 Trace length from DDR2/mDDR device power ball to connection via 35 Mils
7 DDR_DVDD18 Supply HS Bypass Capacitor Count(2) 10 Devices
8 DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance 0.6 μF
9 DDR#1 HS Bypass Capacitor Count(2) 8 Devices
10 DDR#1 HS Bypass Capacitor Total Capacitance 0.4 μF
11 DDR#2 HS Bypass Capacitor Count(2)(3) 8 Devices
12 DDR#2 HS Bypass Capacitor Total Capacitance(3) 0.4 μF
LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
These devices should be placed as close as possible to the device being bypassed.
Only used on dual-memory systems.
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

Net Classes

Table 6-33 lists the clock net classes for the DDR2/mDDR interface. Table 6-34 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow.

Table 6-33 Clock Net Class Definitions

CLOCK NET CLASS Soc PIN NAMES
CK DDR_CLKP / DDR_CLKN
DQS0 DDR_DQS[0]
DQS1 DDR_DQS[1]

Table 6-34 Signal Net Class Definitions

SIGNAL NET CLASS ASSOCIATED CLOCK NET CLASS Soc PIN NAMES
ADDR_CTRL CK DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE
D0 DQS0 DDR_D[7:0], DDR_DQM0
D1 DQS1 DDR_D[15:8], DDR_DQM1
DQGATE CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1

DDR2/mDDR Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-35 shows the specifications for the series terminators.

Table 6-35 DDR2/mDDR Signal Terminations(1)(2)(3)

NO. PARAMETER MIN TYP MAX UNIT
1 CK Net Class 0 10 Ω
2 ADDR_CTRL Net Class 0 22 Zo Ω
3 Data Byte Net Classes (DQS[0], DQS[1], D0, D1)(4) 0 22 Zo Ω
4 DQGATE Net Class (DQGATE) 0 10 Zo Ω
Only series termination is permitted, parallel or SST specifically disallowed.
Terminator values larger than typical only recommended to address EMI issues.
Termination value should be uniform across net class.
When no termination is used on data lines (0 Ω), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.

VREF Routing

VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the OMAP-L138. VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-18. Other methods of creating VREF are not recommended. Figure 6-22 shows the layout guidelines for VREF.

OMAP-L138 figure_4_praar3.gif Figure 6-22 VREF Routing and Topology

DDR2/mDDR CK and ADDR_CTRL Routing

Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

OMAP-L138 f5_praar3.gif Figure 6-23 CK and ADDR_CTRL Routing and Topology

Table 6-36 CK and ADDR_CTRL Routing Specification

NO. PARAMETER MIN TYP MAX UNIT
1 Center to Center CK-CKN Spacing(3) 2w(4)
2 CK A to B/A to C Skew Length Mismatch(1) 25 Mils
3 CK B to C Skew Length Mismatch 25 Mils
4 Center to center CK to other DDR2/mDDR trace spacing(3) 4w(4)
5 CK/ADDR_CTRL nominal trace length(2) CACLM-50 CACLM CACLM+50 Mils
6 ADDR_CTRL to CK Skew Length Mismatch 100 Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils
8 Center to center ADDR_CTRL to other DDR2/mDDR trace spacing(3) 4w(4)
9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing(3) 3w (4)
10 ADDR_CTRL A to B/A to C Skew Length Mismatch(1) 100 Mils
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils
Series terminator, if used, should be located closest to device.
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.
w = PCB trace width as defined in Table 6-29.

Figure 6-24 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended.

OMAP-L138 f6_praar3.gif Figure 6-24 DQS and D Routing and Topology

Table 6-37 DQS and D Routing Specification

NO. PARAMETER MIN TYP MAX UNIT
1 Center to center DQS to other DDR2/mDDR trace spacing(4) 4w(6)
2 DQS/D nominal trace length(1)(3) DQLM-50 DQLM DQLM+50 Mils
3 D to DQS Skew Length Mismatch(3) 100 Mils
4 D to D Skew Length Mismatch(3) 100 Mils
5 Center to center D to other DDR2/mDDR trace spacing(4)(5) 4w(6)
6 Center to Center D to other D trace spacing(4)(2) 3w(6)
Series terminator, if used, should be located closest to DDR.
DQLM is the longest Manhattan distance of each of the DQS and D net class.
There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1.
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.
D's from other DQS domains are considered other DDR2/mDDR trace.
w = PCB trace width as defined in Table 6-29.

Figure 6-25 shows the routing for the DQGATE net class. Table 6-38 contains the routing specification.

OMAP-L138 f12_praar3.gif Figure 6-25 DQGATE Routing

Table 6-38 DQGATE Routing Specification

NO. PARAMETER MIN TYP MAX UNIT
1 DQGATE Length F CKB0B(1)
2 Center to center DQGATE to any other trace spacing 4w(3)
3 DQS/D nominal trace length DQLM-50 DQLM DQLM+50 Mils
4 DQGATE Skew(2) 100 Mils
CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
Skew from CKB0B1
w = PCB trace width as defined in Table 6-29.

DDR2/mDDR Boundary Scan Limitations

Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects between functional and boundary scan paths.

The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output enable cells on the DDR pins and this is a violation of IEEE 1149.1. Full EXTEST and PRELOAD capability is still available.

Memory Protection Units

The MPU performs memory protection checking. It receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. If allowed, the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails the protection check) then the MPU does not pass the transfer to the output bus but rather services the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as well as generating an interrupt about the fault. The following features are supported by the MPU:

  • Provides memory protection for fixed and programmable address ranges.
  • Supports multiple programmable address region.
  • Supports secure and debug access privileges.
  • Supports read, write, and execute access privileges.
  • Supports privid(8) associations with ranges.
  • Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
  • MMR access is also protected.

Table 6-39 MPU1 Configuration Registers

MPU1
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01E1 4000 REVID Revision ID
0x01E1 4004 CONFIG Configuration
0x01E1 4010 IRAWSTAT Interrupt raw status/set
0x01E1 4014 IENSTAT Interrupt enable status/clear
0x01E1 4018 IENSET Interrupt enable
0x01E1 401C IENCLR Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF - Reserved
0x01E1 4200 PROG1_MPSAR Programmable range 1, start address
0x01E1 4204 PROG1_MPEAR Programmable range 1, end address
0x01E1 4208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 420C - 0x01E1 420F - Reserved
0x01E1 4210 PROG2_MPSAR Programmable range 2, start address
0x01E1 4214 PROG2_MPEAR Programmable range 2, end address
0x01E1 4218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 421C - 0x01E1 421F - Reserved
0x01E1 4220 PROG3_MPSAR Programmable range 3, start address
0x01E1 4224 PROG3_MPEAR Programmable range 3, end address
0x01E1 4228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 422C - 0x01E1 422F - Reserved
0x01E1 4230 PROG4_MPSAR Programmable range 4, start address
0x01E1 4234 PROG4_MPEAR Programmable range 4, end address
0x01E1 4238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 423C - 0x01E1 423F - Reserved
0x01E1 4240 PROG5_MPSAR Programmable range 5, start address
0x01E1 4244 PROG5_MPEAR Programmable range 5, end address
0x01E1 4248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 424C - 0x01E1 424F - Reserved
0x01E1 4250 PROG6_MPSAR Programmable range 6, start address
0x01E1 4254 PROG6_MPEAR Programmable range 6, end address
0x01E1 4258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 425C - 0x01E1 42FF - Reserved
0x01E1 4300 FLTADDRR Fault address
0x01E1 4304 FLTSTAT Fault status
0x01E1 4308 FLTCLR Fault clear
0x01E1 430C - 0x01E1 4FFF - Reserved

Table 6-40 MPU2 Configuration Registers

MPU2
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01E1 5000 REVID Revision ID
0x01E1 5004 CONFIG Configuration
0x01E1 5010 IRAWSTAT Interrupt raw status/set
0x01E1 5014 IENSTAT Interrupt enable status/clear
0x01E1 5018 IENSET Interrupt enable
0x01E1 501C IENCLR Interrupt enable clear
0x01E1 5020 - 0x01E1 51FF - Reserved
0x01E1 5200 PROG1_MPSAR Programmable range 1, start address
0x01E1 5204 PROG1_MPEAR Programmable range 1, end address
0x01E1 5208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 520C - 0x01E1 520F - Reserved
0x01E1 5210 PROG2_MPSAR Programmable range 2, start address
0x01E1 5214 PROG2_MPEAR Programmable range 2, end address
0x01E1 5218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 521C - 0x01E1 521F - Reserved
0x01E1 5220 PROG3_MPSAR Programmable range 3, start address
0x01E1 5224 PROG3_MPEAR Programmable range 3, end address
0x01E1 5228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 522C - 0x01E1 522F - Reserved
0x01E1 5230 PROG4_MPSAR Programmable range 4, start address
0x01E1 5234 PROG4_MPEAR Programmable range 4, end address
0x01E1 5238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 523C - 0x01E1 523F - Reserved
0x01E1 5240 PROG5_MPSAR Programmable range 5, start address
0x01E1 5244 PROG5_MPEAR Programmable range 5, end address
0x01E1 5248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 524C - 0x01E1 524F - Reserved
0x01E1 5250 PROG6_MPSAR Programmable range 6, start address
0x01E1 5254 PROG6_MPEAR Programmable range 6, end address
0x01E1 5258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 525C - 0x01E1 525F - Reserved
0x01E1 5260 PROG7_MPSAR Programmable range 7, start address
0x01E1 5264 PROG7_MPEAR Programmable range 7, end address
0x01E1 5268 PROG7_MPPA Programmable range 7, memory page protection attributes
0x01E1 526C - 0x01E1 526F - Reserved
0x01E1 5270 PROG8_MPSAR Programmable range 8, start address
0x01E1 5274 PROG8_MPEAR Programmable range 8, end address
0x01E1 5278 PROG8_MPPA Programmable range 8, memory page protection attributes
0x01E1 527C - 0x01E1 527F - Reserved
0x01E1 5280 PROG9_MPSAR Programmable range 9, start address
0x01E1 5284 PROG9_MPEAR Programmable range 9, end address
0x01E1 5288 PROG9_MPPA Programmable range 9, memory page protection attributes
0x01E1 528C - 0x01E1 528F - Reserved
0x01E1 5290 PROG10_MPSAR Programmable range 10, start address
0x01E1 5294 PROG10_MPEAR Programmable range 10, end address
0x01E1 5298 PROG10_MPPA Programmable range 10, memory page protection attributes
0x01E1 529C - 0x01E1 529F - Reserved
0x01E1 52A0 PROG11_MPSAR Programmable range 11, start address
0x01E1 52A4 PROG11_MPEAR Programmable range 11, end address
0x01E1 52A8 PROG11_MPPA Programmable range 11, memory page protection attributes
0x01E1 52AC - 0x01E1 52AF - Reserved
0x01E1 52B0 PROG12_MPSAR Programmable range 12, start address
0x01E1 52B4 PROG12_MPEAR Programmable range 12, end address
0x01E1 52B8 PROG12_MPPA Programmable range 12, memory page protection attributes
0x01E1 52BC - 0x01E1 52FF - Reserved
0x01E1 5300 FLTADDRR Fault address
0x01E1 5304 FLTSTAT Fault status
0x01E1 5308 FLTCLR Fault clear
0x01E1 530C - 0x01E1 5FFF - Reserved

MMC / SD / SDIO (MMCSD0, MMCSD1)

MMCSD Peripheral Description

The device includes an two MMCSD controllers which are compliant with MMC V4.0, Secure Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.

The MMC/SD Controller have following features:

  • MultiMediaCard (MMC)
  • Secure Digital (SD) Memory Card
  • MMC/SD protocol support
  • SD high capacity support
  • SDIO protocol support
  • Programmable clock frequency
  • 512 bit Read/Write FIFO to lower system overhead
  • Slave EDMA transfer capability

The device MMC/SD Controller does not support SPI mode.

MMCSD Peripheral Register Description(s)

Table 6-41 Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers

MMCSD0
BYTE ADDRESS
MMCSD1
BYTE ADDRESS
ACRONYM REGISTER DESCSRIPTION
0x01C4 0000 0x01E1 B000 MMCCTL MMC Control Register
0x01C4 0004 0x01E1 B004 MMCCLK MMC Memory Clock Control Register
0x01C4 0008 0x01E1 B008 MMCST0 MMC Status Register 0
0x01C4 000C 0x01E1 B00C MMCST1 MMC Status Register 1
0x01C4 0010 0x01E1 B010 MMCIM MMC Interrupt Mask Register
0x01C4 0014 0x01E1 B014 MMCTOR MMC Response Time-Out Register
0x01C4 0018 0x01E1 B018 MMCTOD MMC Data Read Time-Out Register
0x01C4 001C 0x01E1 B01C MMCBLEN MMC Block Length Register
0x01C4 0020 0x01E1 B020 MMCNBLK MMC Number of Blocks Register
0x01C4 0024 0x01E1 B024 MMCNBLC MMC Number of Blocks Counter Register
0x01C4 0028 0x01E1 B028 MMCDRR MMC Data Receive Register
0x01C4 002C 0x01E1 B02C MMCDXR MMC Data Transmit Register
0x01C4 0030 0x01E1 B030 MMCCMD MMC Command Register
0x01C4 0034 0x01E1 B034 MMCARGHL MMC Argument Register
0x01C4 0038 0x01E1 B038 MMCRSP01 MMC Response Register 0 and 1
0x01C4 003C 0x01E1 B03C MMCRSP23 MMC Response Register 2 and 3
0x01C4 0040 0x01E1 B040 MMCRSP45 MMC Response Register 4 and 5
0x01C4 0044 0x01E1 B044 MMCRSP67 MMC Response Register 6 and 7
0x01C4 0048 0x01E1 B048 MMCDRSP MMC Data Response Register
0x01C4 0050 0x01E1 B050 MMCCIDX MMC Command Index Register
0x01C4 0064 0x01E1 B064 SDIOCTL SDIO Control Register
0x01C4 0068 0x01E1 B068 SDIOST0 SDIO Status Register 0
0x01C4 006C 0x01E1 B06C SDIOIEN SDIO Interrupt Enable Register
0x01C4 0070 0x01E1 B070 SDIOIST SDIO Interrupt Status Register
0x01C4 0074 0x01E1 B074 MMCFIFOCTL MMC FIFO Control Register

MMC/SD Electrical Data/Timing

Table 6-42 through Table 6-43 assume testing over recommended operating conditions.

Table 6-42 Timing Requirements for MMC/SD
(see Figure 6-27 and Figure 6-29)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tsu(CMDV-CLKH) Setup time, MMCSD_CMD valid before MMCSD_CLK high 4 4 6 ns
2 th(CLKH-CMDV) Hold time, MMCSD_CMD valid after MMCSD_CLK high 2.5 2.5 2.5 ns
3 tsu(DATV-CLKH) Setup time, MMCSD_DATx valid before MMCSD_CLK high 4.5 5 6 ns
4 th(CLKH-DATV) Hold time, MMCSD_DATx valid after MMCSD_CLK high 2.5 2.5 2.5 ns

Table 6-43 Switching Characteristics for MMC/SD (see Figure 6-26 through Figure 6-29)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
7 f(CLK) Operating frequency, MMCSD_CLK 0 52 0 50 0 25 MHz
8 f(CLK_ID) Identification mode frequency, MMCSD_CLK 0 400 0 400 0 400 KHz
9 tW(CLKL) Pulse width, MMCSD_CLK low 6.5 6.5 10 ns
10 tW(CLKH) Pulse width, MMCSD_CLK high 6.5 6.5 10 ns
11 tr(CLK) Rise time, MMCSD_CLK 3 3 10 ns
12 tf(CLK) Fall time, MMCSD_CLK 3 3 10 ns
13 td(CLKL-CMD) Delay time, MMCSD_CLK low to MMCSD_CMD transition -4 2.5 -4 3 -4 4 ns
14 td(CLKL-DAT) Delay time, MMCSD_CLK low to MMCSD_DATx transition -4 3.3 -4 3.5 -4 4 ns
OMAP-L138 td_mmcsdcmd_prs348.gif Figure 6-26 MMC/SD Host Command Timing
OMAP-L138 td_mmcsdrspn_prs271.gif Figure 6-27 MMC/SD Card Response Timing
OMAP-L138 td_mmcsdwrt_prs348.gif Figure 6-28 MMC/SD Host Write Timing
OMAP-L138 td_mmcsdrdst_prs348.gif Figure 6-29 MMC/SD Host Read and Card CRC Status Timing

Serial ATA Controller (SATA)

The Serial ATA Controller (SATA) provides a single HBA port operating in AHCI mode and is used to interface to data storage devices at both 1.5 Gbits/second and 3.0 Gbits/second line speeds. AHCI describes a system memory structure that contains a generic area for control and status, and a table of entries describing a command list where each command list entry contains information necessary to program an SATA device, and a pointer to a descriptor table for transferring data between system memory and the device.

The SATA Controller supports the following features:

  • Serial ATA 1.5 Gbps (Gen 1i) and 3 Gbps (Gen 2i) line speeds
  • Support for the AHCI controller spec 1.1
  • Integrated SERDES PHY
  • Integrated Rx and Tx data buffers
  • Supports all SATA power management features
  • Internal DMA engine per port
  • Hardware-assisted native command queuing (NCQ) for up to 32 entries
  • 32-bit addressing
  • Supports port multiplier with command-based switching
  • Activity LED support
  • Mechanical presence switch
  • Cold presence detect

The SATA Controller support is dependent on the CPU voltage operating point:

  • At CVDD = 1.3V, SATA Gen 2i (3.0 Gbps) and SATA Gen 1i (1.5 Gbps) are supported.
  • At CVDD = 1.2V, SATA Gen 2i (3.0 Gbps) and SATA Gen 1i (1.5 Gbps) are supported.
  • At CVDD = 1.1V, SATA Gen 1i (1.5 Gbps) only is supported.
  • At CVDD = 1.0V, SATA is not supported.

SATA Register Descriptions

Table 6-44 is a list of the SATA Controller registers.

Table 6-44 SATA Controller Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E1 8000 CAP HBA Capabilities Register
0x01E1 8004 GHC Global HBA Control Register
0x01E1 8008 IS Interrupt Status Register
0x01E1 800C PI Ports Implemented Register
0x01E1 8010 VS AHCI Version Register
0x01E1 8014 CCC_CTL Command Completion Coalescing Control Register
0x01E1 8018 CCC_PORTS Command Completion Coalescing Ports Register
0x01E1 80A0 BISTAFR BIST Active FIS Register
0x01E1 80A4 BISTCR BIST Control Register
0x01E1 80A8 BISTFCTR BIST FIS Count Register
0x01E1 80AC BISTSR BIST Status Register
0x01E1 80B0 BISTDECR BIST DWORD Error Count Register
0x01E1 80E0 TIMER1MS BIST DWORD Error Count Register
0x01E1 80E8 GPARAM1R Global Parameter 1 Register
0x01E1 80EC GPARAM2R Global Parameter 2 Register
0x01E1 80F0 PPARAMR Port Parameter Register
0x01E1 80F4 TESTR Test Register
0x01E1 80F8 VERSIONR Version Register
0x01E1 80FC IDR ID Register
0x01E1 8100 P0CLB Port Command List Base Address Register
0x01E1 8108 P0FB Port FIS Base Address Register
0x01E1 8110 P0IS Port Interrupt Status Register
0x01E1 8114 P0IE Port Interrupt Enable Register
0x01E1 8118 P0CMD Port Command Register
0x01E1 8120 P0TFD Port Task File Data Register
0x01E1 8124 P0SIG Port Signature Register
0x01E1 8128 P0SSTS Port Serial ATA Status Register
0x01E1 812C P0SCTL Port Serial ATA Control Register
0x01E1 8130 P0SERR Port Serial ATA Error Register
0x01E1 8134 P0SACT Port Serial ATA Active Register
0x01E1 8138 P0CI Port Command Issue Register
0x01E1 813C P0SNTF Port Serial ATA Notification Register
0x01E1 8170 P0DMACR Port DMA Control Register
0x01E1 8178 P0PHYCR Port PHY Control Register
0x01E1 817C P0PHYSR Port PHY Status Register

1. SATA Interface

This section provides the timing specification for the SATA interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to ensure the SATA interface requirements are met.

SATA Interface Schematic

Figure 6-30 shows the SATA interface schematic.

OMAP-L138 fre_SATA_hl_Sch_prs588.gif Figure 6-30 SATA Interface High Level Schematic

Compatible SATA Components and Modes

Table 6-45 shows the compatible SATA components and supported modes. Note that the only supported configuration is an internal cable from the processor host to the SATA device.

Table 6-45 SATA Supported Modes

PARAMETER MIN MAX UNIT SUPPORTED
Transfer Rates 1.5 3.0 Gbps
eSATA No
xSATA No
Backplane No
Internal Cable Yes

PCB Stackup Specifications

Table 6-46 shows the stackup and feature sizes required for SATA.

Table 6-46 SATA PCB Stackup Specifications

PARAMETER MIN TYP MAX UNIT
PCB Routing/Plane Layers 4 6 Layers
Signal Routing Layers 2 3 Layers
Number of ground plane cuts allowed within SATA routing region 0 Layers
Number of layers between SATA routing region and reference ground plane 0
PCB Routing Feature Size 4 Mils
PCB Trace Width w 4 Mils
PCB BGA escape via pad size 18 Mils
PCB BGA escape via hole size 8 Mils
Device BGA pad size (1)
Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.

Routing Specifications

The SATA data signal traces are edge-coupled and must be routed to achieve exactly 100 Ohms differential impedance. This is impacted by trace width, trace spacing, distance between planes, and dielectric material. Verify with a proper PCB manufacturing tool that the trace geometry for both data signal pairs results in exactly 100 ohms differential impedance traces. Table 6-47 shows the routing specifications for the data and REFCLK signals.

Table 6-47 SATA Routing Specifications

PARAMETER MIN TYP MAX UNIT
Device to SATA header trace length 7000 Mils
REFCLK trace length from oscillator to Device(3) 2000 Mils
Number of stubs allowed on SATA traces 0 Stubs
TX/RX pair differential impedance 100 Ohms
Number of vias on each SATA trace 3 Vias (1)
SATA differential pair to any other trace spacing 2*DS (2)
Vias must be used in pairs with their distance minimized.
DS is the differential spacing of the SATA traces.
The SATA_REFCLK(P/N) pins include an internal 100 Ohms differential termination

Coupling Capacitors

AC coupling capacitors are required on the receive data pair as well as the REFCLK pair. Table 6-48 shows the requirements for these capacitors.

Table 6-48 SATA Bypass and Coupling Capacitors Requirements

PARAMETER MIN TYP MAX UNIT
SATA AC coupling capacitor value 0.3 10 12 nF
SATA AC coupling capacitor package size 0603 10 Mils(1)(2)
LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor.
The physical size of the capacitor should be as small as possible.

SATA Interface Clock Source requirements

A high-quality, low-jitter differential clock source is required for the SATA PHY. The SATA interface requires a LVDS differential clock source to be provided at signals SATA_REFCLKP and SATA_REFCLKN. The clock source should be placed physically as close to the processor as possible.

Table 6-49 shows the requirements for the clock source.

Table 6-49 SATA Input Clock Source Requirements

PARAMETER MIN TYP MAX UNIT
Clock Frequency (1) 75 375 MHz
Jitter 50 ps pk-pk
Duty Cycle 40 60 %
Rise/Fall Time 700 ps
Discrete clock frequency points are supported based on the PLL multiplier used in the SATA PHY.

SATA Unused Signal Configuration

If the SATA interface is not used, the SATA signals should be configured as shown below.

Table 6-50 Unused SATA Signal Configuration

SATA Signal Name Configuration if SATA peripheral is not used
SATA_RXP No Connect
SATA_RXN No Connect
SATA_TXP No Connect
SATA_TXN No Connect
SATA_REFCLKP No Connect
SATA_REFCLKN No Connect
SATA_MPSWITCH May be used as GPIO or other peripheral function
SATA_CP_DET May be used as GPIO or other peripheral function
SATA_CP_POD May be used as GPIO or other peripheral function
SATA_LED May be used as GPIO or other peripheral function
SATA_REG No Connect
SATA_VDDR No Connect
SATA_VDD Prior to silicon revision 2.0, this supply must be connected to a static 1.2V nominal supply. For silicon revision 2.0 and later, this supply may be left unconnected for additional power conservation.
SATA_VSS Vss

Multichannel Audio Serial Port (McASP)

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:

  • Flexible clock and frame sync generation logic and on-chip dividers
  • Up to sixteen transmit or receive data pins and serializers
  • Large number of serial data format options, including:
    • TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
    • Time slots of 8,12,16, 20, 24, 28, and 32 bits
    • First bit delay 0, 1, or 2 clocks
    • MSB or LSB first bit order
    • Left- or right-aligned data words within time slots
  • DIT Mode with 384-bit Channel Status and 384-bit User Data registers
  • Extensive error checking and mute generation logic
  • All unused pins GPIO-capable

  • Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it more tolerant to DMA latency.
  • Dynamic Adjustment of Clock Dividers
    • Clock Divider Value may be changed without resetting the McASP

OMAP-L138 mcasp_bd_prs586.gif Figure 6-31 McASP Block Diagram

McASP Peripheral Registers Description(s)

Registers for the McASP are summarized in Table 6-51. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-52

Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-53. Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port.

Table 6-51 McASP Registers Accessed Through Peripheral Configuration Port

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01D0 0000 REV Revision identification register
0x01D0 0010 PFUNC Pin function register
0x01D0 0014 PDIR Pin direction register
0x01D0 0018 PDOUT Pin data output register
0x01D0 001C PDIN Read returns: Pin data input register
0x01D0 001C PDSET Writes affect: Pin data set register (alternate write address: PDOUT)
0x01D0 0020 PDCLR Pin data clear register (alternate write address: PDOUT)
0x01D0 0044 GBLCTL Global control register
0x01D0 0048 AMUTE Audio mute control register
0x01D0 004C DLBCTL Digital loopback control register
0x01D0 0050 DITCTL DIT mode control register
0x01D0 0060 RGBLCTL Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitter
0x01D0 0064 RMASK Receive format unit bit mask register
0x01D0 0068 RFMT Receive bit stream format register
0x01D0 006C AFSRCTL Receive frame sync control register
0x01D0 0070 ACLKRCTL Receive clock control register
0x01D0 0074 AHCLKRCTL Receive high-frequency clock control register
0x01D0 0078 RTDM Receive TDM time slot 0-31 register
0x01D0 007C RINTCTL Receiver interrupt control register
0x01D0 0080 RSTAT Receiver status register
0x01D0 0084 RSLOT Current receive TDM time slot register
0x01D0 0088 RCLKCHK Receive clock check control register
0x01D0 008C REVTCTL Receiver DMA event control register
0x01D0 00A0 XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiver
0x01D0 00A4 XMASK Transmit format unit bit mask register
0x01D0 00A8 XFMT Transmit bit stream format register
0x01D0 00AC AFSXCTL Transmit frame sync control register
0x01D0 00B0 ACLKXCTL Transmit clock control register
0x01D0 00B4 AHCLKXCTL Transmit high-frequency clock control register
0x01D0 00B8 XTDM Transmit TDM time slot 0-31 register
0x01D0 00BC XINTCTL Transmitter interrupt control register
0x01D0 00C0 XSTAT Transmitter status register
0x01D0 00C4 XSLOT Current transmit TDM time slot register
0x01D0 00C8 XCLKCHK Transmit clock check control register
0x01D0 00CC XEVTCTL Transmitter DMA event control register
0x01D0 0100 DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0
0x01D0 0104 DITCSRA1 Left (even TDM time slot) channel status register (DIT mode) 1
0x01D0 0108 DITCSRA2 Left (even TDM time slot) channel status register (DIT mode) 2
0x01D0 010C DITCSRA3 Left (even TDM time slot) channel status register (DIT mode) 3
0x01D0 0110 DITCSRA4 Left (even TDM time slot) channel status register (DIT mode) 4
0x01D0 0114 DITCSRA5 Left (even TDM time slot) channel status register (DIT mode) 5
0x01D0 0118 DITCSRB0 Right (odd TDM time slot) channel status register (DIT mode) 0
0x01D0 011C DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 1
0x01D0 0120 DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 2
0x01D0 0124 DITCSRB3 Right (odd TDM time slot) channel status register (DIT mode) 3
0x01D0 0128 DITCSRB4 Right (odd TDM time slot) channel status register (DIT mode) 4
0x01D0 012C DITCSRB5 Right (odd TDM time slot) channel status register (DIT mode) 5
0x01D0 0130 DITUDRA0 Left (even TDM time slot) channel user data register (DIT mode) 0
0x01D0 0134 DITUDRA1 Left (even TDM time slot) channel user data register (DIT mode) 1
0x01D0 0138 DITUDRA2 Left (even TDM time slot) channel user data register (DIT mode) 2
0x01D0 013C DITUDRA3 Left (even TDM time slot) channel user data register (DIT mode) 3
0x01D0 0140 DITUDRA4 Left (even TDM time slot) channel user data register (DIT mode) 4
0x01D0 0144 DITUDRA5 Left (even TDM time slot) channel user data register (DIT mode) 5
0x01D0 0148 DITUDRB0 Right (odd TDM time slot) channel user data register (DIT mode) 0
0x01D0 014C DITUDRB1 Right (odd TDM time slot) channel user data register (DIT mode) 1
0x01D0 0150 DITUDRB2 Right (odd TDM time slot) channel user data register (DIT mode) 2
0x01D0 0154 DITUDRB3 Right (odd TDM time slot) channel user data register (DIT mode) 3
0x01D0 0158 DITUDRB4 Right (odd TDM time slot) channel user data register (DIT mode) 4
0x01D0 015C DITUDRB5 Right (odd TDM time slot) channel user data register (DIT mode) 5
0x01D0 0180 SRCTL0 Serializer control register 0
0x01D0 0184 SRCTL1 Serializer control register 1
0x01D0 0188 SRCTL2 Serializer control register 2
0x01D0 018C SRCTL3 Serializer control register 3
0x01D0 0190 SRCTL4 Serializer control register 4
0x01D0 0194 SRCTL5 Serializer control register 5
0x01D0 0198 SRCTL6 Serializer control register 6
0x01D0 019C SRCTL7 Serializer control register 7
0x01D0 01A0 SRCTL8 Serializer control register 8
0x01D0 01A4 SRCTL9 Serializer control register 9
0x01D0 01A8 SRCTL10 Serializer control register 10
0x01D0 01AC SRCTL11 Serializer control register 11
0x01D0 01B0 SRCTL12 Serializer control register 12
0x01D0 01B4 SRCTL13 Serializer control register 13
0x01D0 01B8 SRCTL14 Serializer control register 14
0x01D0 01BC SRCTL15 Serializer control register 15
0x01D0 0200 XBUF0(1) Transmit buffer register for serializer 0
0x01D0 0204 XBUF1(1) Transmit buffer register for serializer 1
0x01D0 0208 XBUF2(1) Transmit buffer register for serializer 2
0x01D0 020C XBUF3(1) Transmit buffer register for serializer 3
0x01D0 0210 XBUF4(1) Transmit buffer register for serializer 4
0x01D0 0214 XBUF5(1) Transmit buffer register for serializer 5
0x01D0 0218 XBUF6(1) Transmit buffer register for serializer 6
0x01D0 021C XBUF7(1) Transmit buffer register for serializer 7
0x01D0 0220 XBUF8(1) Transmit buffer register for serializer 8
0x01D0 0224 XBUF9(1) Transmit buffer register for serializer 9
0x01D0 0228 XBUF10(1) Transmit buffer register for serializer 10
0x01D0 022C XBUF11(1) Transmit buffer register for serializer 11
0x01D0 0230 XBUF12(1) Transmit buffer register for serializer 12
0x01D0 0234 XBUF13(1) Transmit buffer register for serializer 13
0x01D0 0238 XBUF14(1) Transmit buffer register for serializer 14
0x01D0 023C XBUF15(1) Transmit buffer register for serializer 15
0x01D0 0280 RBUF0(2) Receive buffer register for serializer 0
0x01D0 0284 RBUF1(2) Receive buffer register for serializer 1
0x01D0 0288 RBUF2(2) Receive buffer register for serializer 2
0x01D0 028C RBUF3(2) Receive buffer register for serializer 3
0x01D0 0290 RBUF4(2) Receive buffer register for serializer 4
0x01D0 0294 RBUF5(2) Receive buffer register for serializer 5
0x01D0 0298 RBUF6(2) Receive buffer register for serializer 6
0x01D0 029C RBUF7(2) Receive buffer register for serializer 7
0x01D0 02A0 RBUF8(2) Receive buffer register for serializer 8
0x01D0 02A4 RBUF9(2) Receive buffer register for serializer 9
0x01D0 02A8 RBUF10(2) Receive buffer register for serializer 10
0x01D0 02AC RBUF11(2) Receive buffer register for serializer 11
0x01D0 02B0 RBUF12(2) Receive buffer register for serializer 12
0x01D0 02B4 RBUF13(2) Receive buffer register for serializer 13
0x01D0 02B8 RBUF14(2) Receive buffer register for serializer 14
0x01D0 02BC RBUF15(2) Receive buffer register for serializer 15
Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.

Table 6-52 McASP Registers Accessed Through DMA Port

ACCESS TYPE BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
Read Accesses 0x01D0 2000 RBUF Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if XBUSEL = 0 in XFMT.
Write Accesses 0x01D0 2000 XBUF Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0 in RFMT.

Table 6-53 McASP AFIFO Registers Accessed Through Peripheral Configuration Port

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01D0 1000 AFIFOREV AFIFO revision identification register
0x01D0 1010 WFIFOCTL Write FIFO control register
0x01D0 1014 WFIFOSTS Write FIFO status register
0x01D0 1018 RFIFOCTL Read FIFO control register
0x01D0 101C RFIFOSTS Read FIFO status register

McASP Electrical Data/Timing

Multichannel Audio Serial Port 0 (McASP0) Timing

Table 6-54 and Table 6-56 assume testing over recommended operating conditions (see Figure 6-32 and Figure 6-33).

Table 6-54 Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)(2)(5)

NO. 1.3V, 1.2V 1.1V UNIT
MIN MAX MIN MAX
1 tc(AHCLKRX) Cycle time, AHCLKR/X 25 28 ns
2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 12.5 14 ns
3 tc(ACLKRX) Cycle time, ACLKR/X AHCLKR/X ext 25(1) 28(1) ns
4 tw(ACLKRX) Pulse duration, ACLKR/W high or low AHCLKR/X ext 12.5 14 ns
5 tsu(AFSRX-ACLKRX) Setup time,
AFSR/X input to ACLKR/X(3)
AHCLKR/X int 11.5 12 ns
AHCLKR/X ext input 4 5 ns
AHCLKR/X ext output 4 5 ns
6 th(ACLKRX-AFSRX) Hold time,
AFSR/X input after ACLKR/X(3)
AHCLKR/X int -1 -2 ns
AHCLKR/X ext input 1 1 ns
AHCLKR/X ext output 1 1 ns
7 tsu(AXR-ACLKRX) Setup time,
AXR0[n] input to ACLKR/X(3)(4)
AHCLKR/X int 11.5 12 ns
AHCLKR/X ext 4 5 ns
8 th(ACLKRX-AXR) Hold time,
AXR0[n] input after ACLKR/X(3)(4)
AHCLKR/X int -1 -2 ns
AHCLKR/X ext input 3 4 ns
AHCLKR/X ext output 3 4 ns
This timing is limited by the timing shown or 2P, whichever is greater.
ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
P = SYSCLK2 period

Table 6-55 Timing Requirements for McASP0 (1.0V)(2)(5)

NO. 1.0V UNIT
MIN MAX
1 tc(AHCLKRX) Cycle time, AHCLKR/X 35 ns
2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 17.5 ns
3 tc(ACLKRX) Cycle time, ACLKR/X AHCLKR/X ext 35(1) ns
4 tw(ACLKRX) Pulse duration, ACLKR/W high or low AHCLKR/X ext 17.5 ns
5 tsu(AFSRX-ACLKRX) Setup time,
AFSR/X input to ACLKR/X(3)
AHCLKR/X int 16 ns
AHCLKR/X ext input 5.5 ns
AHCLKR/X ext output 5.5 ns
6 th(ACLKRX-AFSRX) Hold time,
AFSR/X input after ACLKR/X(3)
AHCLKR/X int -2 ns
AHCLKR/X ext input 1 ns
AHCLKR/X ext output 1 ns
7 tsu(AXR-ACLKRX) Setup time,
AXR0[n] input to ACLKR/X(3)(4)
AHCLKR/X int 16 ns
AHCLKR/X ext 5.5 ns
8 th(ACLKRX-AXR) Hold time,
AXR0[n] input after ACLKR/X(3)(4)
AHCLKR/X int -2 ns
AHCLKR/X ext input 5 ns
AHCLKR/X ext output 5 ns
This timing is limited by the timing shown or 2P, whichever is greater.
ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
P = SYSCLK2 period

Table 6-56 Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)(1)

NO. PARAMETER 1.3V, 1.2V 1.1V UNIT
MIN MAX MIN MAX
9 tc(AHCLKRX) Cycle time, AHCLKR/X 25 28 ns
10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low AH – 2.5(2) AH – 2.5(2) ns
11 tc(ACLKRX) Cycle time, ACLKR/X ACLKR/X int 25(4)(5) 28(4)(5) ns
12 tw(ACLKRX) Pulse duration, ACLKR/X high or low ACLKR/X int A – 2.5(3) A – 2.5(3) ns
13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid(6) ACLKR/X int -1 6 -1 8 ns
ACLKR/X ext input 2 13.5 2 14.5 ns
ACLKR/X ext output 2 13.5 2 14.5 ns
14 td(ACLKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int -1 6 -1 8 ns
ACLKR/X ext input 2 13.5 2 15 ns
ACLKR/X ext output 2 13.5 2 15 ns
15 tdis(ACLKX-AXRHZ) Disable time, ACLKR/X transmit edge to AXR high impedance following last data bit ACLKR/X int 0 6 0 8 ns
ACLKR/X ext 2 13.5 2 15 ns
McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
P = SYSCLK2 period
This timing is limited by the timing shown or 2P, whichever is greater.
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

Table 6-57 Switching Characteristics for McASP0 (1.0V)(1)

NO. PARAMETER 1.0V UNIT
MIN MAX
9 tc(AHCLKRX) Cycle time, AHCLKR/X 35 ns
10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low AH – 2.5(2) ns
11 tc(ACLKRX) Cycle time, ACLKR/X ACLKR/X int 35(4)(5) ns
12 tw(ACLKRX) Pulse duration, ACLKR/X high or low ACLKR/X int A – 2.5(3) ns
13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid(6) ACLKR/X int -0.5 10 ns
ACLKR/X ext input 2 19 ns
ACLKR/X ext output 2 19 ns
14 td(ACLKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int -0.5 10 ns
ACLKR/X ext input 2 19 ns
ACLKR/X ext output 2 19 ns
15 tdis(ACLKX-AXRHZ) Disable time, ACLKR/X transmit edge to AXR high impedance following last data bit ACLKR/X int 0 10 ns
ACLKR/X ext 2 19 ns
McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
P = SYSCLK2 period
This timing is limited by the timing shown or 2P, whichever is greater.
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
OMAP-L138 td_mcasp_it_prs279.gif
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).
Figure 6-32 McASP Input Timings
OMAP-L138 td_mcasp_ot_prs279.gif
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).
Figure 6-33 McASP Output Timings

Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

  • Full-duplex communication
  • Double-buffered data registers, which allow a continuous data stream
  • Independent framing and clocking for receive and transmit
  • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
  • External shift clock or an internal, programmable frequency shift clock for data transfer
  • Transmit & Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it more tolerant to DMA latency

If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.

McBSP Peripheral Register Description(s)

Table 6-58 McBSP/FIFO Registers

McBSP0
BYTE ADDRESS
McBSP1
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
McBSP Registers
0x01D1 0000 0x01D1 1000 DRR McBSP Data Receive Register (read-only)
0x01D1 0004 0x01D1 1004 DXR McBSP Data Transmit Register
0x01D1 0008 0x01D1 1008 SPCR McBSP Serial Port Control Register
0x01D1 000C 0x01D1 100C RCR McBSP Receive Control Register
0x01D1 0010 0x01D1 1010 XCR McBSP Transmit Control Register
0x01D1 0014 0x01D1 1014 SRGR McBSP Sample Rate Generator register
0x01D1 0018 0x01D1 1018 MCR McBSP Multichannel Control Register
0x01D1 001C 0x01D1 101C RCERE0 McBSP Enhanced Receive Channel Enable Register 0 Partition A/B
0x01D1 0020 0x01D1 1020 XCERE0 McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B
0x01D1 0024 0x01D1 1024 PCR McBSP Pin Control Register
0x01D1 0028 0x01D1 1028 RCERE1 McBSP Enhanced Receive Channel Enable Register 1 Partition C/D
0x01D1 002C 0x01D1 102C XCERE1 McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D
0x01D1 0030 0x01D1 1030 RCERE2 McBSP Enhanced Receive Channel Enable Register 2 Partition E/F
0x01D1 0034 0x01D1 1034 XCERE2 McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F
0x01D1 0038 0x01D1 1038 RCERE3 McBSP Enhanced Receive Channel Enable Register 3 Partition G/H
0x01D1 003C 0x01D1 103C XCERE3 McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H
McBSP FIFO Control and Status Registers
0x01D1 0800 0x01D1 1800 BFIFOREV BFIFO Revision Identification Register
0x01D1 0810 0x01D1 1810 WFIFOCTL Write FIFO Control Register
0x01D1 0814 0x01D1 1814 WFIFOSTS Write FIFO Status Register
0x01D1 0818 0x01D1 1818 RFIFOCTL Read FIFO Control Register
0x01D1 081C 0x01D1 181C RFIFOSTS Read FIFO Status Register
McBSP FIFO Data Registers
0x01F1 0000 0x01F1 1000 RBUF McBSP FIFO Receive Buffer
0x01F1 0000 0x01F1 1000 XBUF McBSP FIFO Transmit Buffer

McBSP Electrical Data/Timing

The following assume testing over recommended operating conditions.

Multichannel Buffered Serial Port (McBSP) Timing

Table 6-59 Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V](1) (see Figure 6-34)

NO. 1.3V, 1.2V 1.1V UNIT
MIN MAX MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P or 20(2)(3) 2P or 25(2)(3) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P - 1(4) P - 1(4) ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 14 15.5 ns
CLKR ext 4 5
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 6 6 ns
CLKR ext 3 3
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 14 15.5 ns
CLKR ext 4 5
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 3 3 ns
CLKR ext 3 3
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 14 15.5 ns
CLKX ext 4 5
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 6 6 ns
CLKX ext 3 3
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-60 Timing Requirements for McBSP0 [1.0V](1) (see Figure 6-34)

NO. 1.0V UNIT
MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P or 26.6(2)(3) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P - 1(4) ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 20 ns
CLKR ext 5
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 6 ns
CLKR ext 3
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 20 ns
CLKR ext 5
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 3 ns
CLKR ext 3
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 20 ns
CLKX ext 5
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 6 ns
CLKX ext 3
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-61 Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V](1)(2)
(see Figure 6-34)

NO. PARAMETER 1.3V, 1.2V 1.1V UNIT
MIN MAX MIN MAX
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 14.5 2 16 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 20(3)(4)(5) 2P or 25(3)(4)(5) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2(6) C + 2(6) C - 2(6) C + 2(6) ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -4 5.5 -4 5.5 ns
CLKR ext 2 14.5 2 16
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int -4 5.5 -4 5.5 ns
CLKX ext 2 14.5 2 16
12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX int -4 7.5 -5.5 7.5 ns
CLKX ext -2 16 -22 16
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX int -4 + D1(7) 5.5 + D2(7) -4 + D1(7) 5.5 + D2(7) ns
CLKX ext 2 + D1(7) 14.5 + D2(7) 2 + D1(7) 16 + D2(7)
14 td(FXH-DXV) Delay time, FSX high to DX valid
FSX int -4(8) 5(8) -4(8) 5(8) ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext -2(8) 14.5(8) -2(8) 16(8)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-62 Switching Characteristics for McBSP0 [1.0V](1) (2)
(see Figure 6-34)

NO. PARAMETER 1.0V UNIT
MIN MAX
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 3 21.5 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 26.6(3)(3)(4) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2(5) C + 2(5) ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -4 10 ns
CLKR ext 2.5 21.5
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int -4 10 ns
CLKX ext 2.5 21.5
12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX int -4 10 ns
CLKX ext -2 21.5
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX int -4 + D1(6) 10 + D2(6) ns
CLKX ext 2.5 + D1(6) 21.5 + D2(6)
14 td(FXH-DXV) Delay time, FSX high to DX valid
FSX int -4(7) 5(7) ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext -2(7) 21.5(7)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-63 Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V](1) (see Figure 6-34)

NO. 1.3V, 1.2V 1.1V UNIT
MIN MAX MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P or 20(2)(3) 2P or 25(2) (3) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P - 1(4) P - 1(4) ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 15 18 ns
CLKR ext 5 5
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 6 6 ns
CLKR ext 3 3
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 15 18 ns
CLKR ext 5 5
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 3 3 ns
CLKR ext 3 3
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 15 18 ns
CLKX ext 5 5
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 6 6 ns
CLKX ext 3 3
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-64 Timing Requirements for McBSP1 [1.0V](1) (see Figure 6-34)

NO. 1.0V UNIT
MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P or 26.6(2)(3) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P - 1(4) ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 21 ns
CLKR ext 10
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 6 ns
CLKR ext 3
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 21 ns
CLKR ext 10
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 3 ns
CLKR ext 3
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 21 ns
CLKX ext 10
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 6 ns
CLKX ext 3
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-65 Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V](1) (2)
(see Figure 6-34)

NO. PARAMETER 1.3V, 1.2V 1.1V UNIT
MIN MAX MIN MAX
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 0.5 16.5 1.5 18 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 20(3)(3)(4) 2P or 25(3)(3) (4) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2(5) C + 2(5) C - 2(5) C + 2(5) ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -4 6.5 -4 13 ns
CLKR ext 1 16.5 1 18
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int -4 6.5 -4 13 ns
CLKX ext 1 16.5 1 18
12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX int -4 6.5 -4 13 ns
CLKX ext -2 16.5 -2 18
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX int -4 + D1(6) 6.5 + D2(6) -4 + D1(6) 13 + D2(6) ns
CLKX ext 1 + D1(6) 16.5 + D2(6) 1 + D1(6) 18 + D2(6)
14 td(FXH-DXV) Delay time, FSX high to DX valid
FSX int -4(7) 6.5(7) -4(7) 13(7) ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext -2(7) 16.5(7) -2(7) 18(8)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-66 Switching Characteristics for McBSP1 [1.0V](1) (2)
(see Figure 6-34)

NO. PARAMETER 1.0V UNIT
MIN MAX
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 1.5 23 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 26.6(3)(4)(5) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2(6) C + 2(6) ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -4 13 ns
CLKR ext 2.5 23
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int -4 13 ns
CLKX ext 1 23
12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX int -4 13 ns
CLKX ext -2 23
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX int -4 + D1(6) 13 + D2(7) ns
CLKX ext 1 + D1(7) 23 + D2(7)
14 td(FXH-DXV) Delay time, FSX high to DX valid
FSX int -4(8) 13(8) ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext -2(8) 23(8)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
Use whichever value is greater.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
OMAP-L138 td_mcbsp_prs345.gif
No. 13 applies to the first data bit only when XDATDLY ≠ 0.
Figure 6-34 McBSP Timing

Table 6-67 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-35)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 4.5 5 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 4 4 ns

Table 6-68 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-35)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 5 5 10 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 4 4 ns
OMAP-L138 td_fsr_prs345.gif Figure 6-35 FSR Timing When GSYNC = 1

Serial Peripheral Interface Ports (SPI0, SPI1)

Figure 6-36 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many data formatting options.

OMAP-L138 bd_spi_prs279.gif Figure 6-36 Block Diagram of SPI Module

The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).

The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin when SPIx_SCS is held low.

In slave mode, SPIx_ENA is an optional output. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the same SPI bus.

In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI communications and, on average, increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer can begin as soon as both the master and slave have actually serviced the previous SPI transfer.

OMAP-L138 spi_mstr_slv_prs279.gif Figure 6-37 Illustration of SPI Master-to-SPI Slave Connection

SPI Peripheral Registers Description(s)

Table 6-69 is a list of the SPI registers.

Table 6-69 SPIx Configuration Registers

SPI0
BYTE ADDRESS
SPI1
BYTE ADDRESS
ACRONYM DESCRIPTION
0x01C4 1000 0x01F0 E000 SPIGCR0 Global Control Register 0
0x01C4 1004 0x01F0 E004 SPIGCR1 Global Control Register 1
0x01C4 1008 0x01F0 E008 SPIINT0 Interrupt Register
0x01C4 100C 0x01F0 E00C SPILVL Interrupt Level Register
0x01C4 1010 0x01F0 E010 SPIFLG Flag Register
0x01C4 1014 0x01F0 E014 SPIPC0 Pin Control Register 0 (Pin Function)
0x01C4 1018 0x01F0 E018 SPIPC1 Pin Control Register 1 (Pin Direction)
0x01C4 101C 0x01F0 E01C SPIPC2 Pin Control Register 2 (Pin Data In)
0x01C4 1020 0x01F0 E020 SPIPC3 Pin Control Register 3 (Pin Data Out)
0x01C4 1024 0x01F0 E024 SPIPC4 Pin Control Register 4 (Pin Data Set)
0x01C4 1028 0x01F0 E028 SPIPC5 Pin Control Register 5 (Pin Data Clear)
0x01C4 102C 0x01F0 E02C Reserved Reserved - Do not write to this register
0x01C4 1030 0x01F0 E030 Reserved Reserved - Do not write to this register
0x01C4 1034 0x01F0 E034 Reserved Reserved - Do not write to this register
0x01C4 1038 0x01F0 E038 SPIDAT0 Shift Register 0 (without format select)
0x01C4 103C 0x01F0 E03C SPIDAT1 Shift Register 1 (with format select)
0x01C4 1040 0x01F0 E040 SPIBUF Buffer Register
0x01C4 1044 0x01F0 E044 SPIEMU Emulation Register
0x01C4 1048 0x01F0 E048 SPIDELAY Delay Register
0x01C4 104C 0x01F0 E04C SPIDEF Default Chip Select Register
0x01C4 1050 0x01F0 E050 SPIFMT0 Format Register 0
0x01C4 1054 0x01F0 E054 SPIFMT1 Format Register 1
0x01C4 1058 0x01F0 E058 SPIFMT2 Format Register 2
0x01C4 105C 0x01F0 E05C SPIFMT3 Format Register 3
0x01C4 1060 0x01F0 E060 INTVEC0 Interrupt Vector for SPI INT0
0x01C4 1064 0x01F0 E064 INTVEC1 Interrupt Vector for SPI INT1

SPI Electrical Data/Timing

Serial Peripheral Interface (SPI) Timing

Table 6-70 through Table 6-85 assume testing over recommended operating conditions (see Figure 6-38 through Figure 6-41).

Table 6-70 General Timing Requirements for SPI0 Master Modes(1)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tc(SPC)M Cycle Time, SPI0_CLK, All Master Modes 20(2) 256P 30(2) 256P 40(2) 256P ns
2 tw(SPCH)M Pulse Width High, SPI0_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns
3 tw(SPCL)M Pulse Width Low, SPI0_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns
4 td(SIMO_SPC)M Delay, initial data bit valid on SPI0_SIMO after initial edge on SPI0_CLK(3) Polarity = 0, Phase = 0,
to SPI0_CLK rising
5 5 6 ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
-0.5M+5 -0.5M+5 -0.5M+6
Polarity = 1, Phase = 0,
to SPI0_CLK falling
5 5 6
Polarity = 1, Phase = 1,
to SPI0_CLK falling
-0.5M+5 -0.5M+5 -0.5M+6
5 td(SPC_SIMO)M Delay, subsequent bits valid on SPI0_SIMO after transmit edge of SPI0_CLK Polarity = 0, Phase = 0,
from SPI0_CLK rising
5 5 6 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
5 5 6
Polarity = 1, Phase = 0,
from SPI0_CLK falling
5 5 6
Polarity = 1, Phase = 1,
from SPI0_CLK rising
5 5 6
6 toh(SPC_SIMO)M Output hold time, SPI0_SIMO valid after receive edge of SPI0_CLK Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M-3 0.5M-3 0.5M-3 ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5M-3 0.5M-3 0.5M-3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M-3 0.5M-3 0.5M-3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5M-3 0.5M-3 0.5M-3
7 tsu(SOMI_SPC)M Input Setup Time, SPI0_SOMI valid before receive edge of SPI0_CLK Polarity = 0, Phase = 0,
to SPI0_CLK falling
1.5 1.5 1.5 ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 0,
to SPI0_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.5 1.5 1.5
8 tih(SPC_SOMI)M Input Hold Time, SPI0_SOMI valid after receive edge of SPI0_CLK Polarity = 0, Phase = 0,
from SPI0_CLK falling
4 4 5 ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
4 4 5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
4 4 5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
4 4 5
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
This timing is limited by the timing shown or 3P, whichever is greater.
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.

Table 6-71 General Timing Requirements for SPI0 Slave Modes(1)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
9 tc(SPC)S Cycle Time, SPI0_CLK, All Slave Modes 40(2) 50(2) 60(2) ns
10 tw(SPCH)S Pulse Width High, SPI0_CLK, All Slave Modes 18 22 27 ns
11 tw(SPCL)S Pulse Width Low, SPI0_CLK, All Slave Modes 18 22 27 ns
12 tsu(SOMI_SPC)S Setup time, transmit data written to SPI before initial clock edge from
master.(3) (4)
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P 2P 2P ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
2P 2P 2P
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P 2P 2P
Polarity = 1, Phase = 1,
to SPI0_CLK falling
2P 2P 2P
13 td(SPC_SOMI)S Delay, subsequent bits valid on SPI0_SOMI after transmit edge of SPI0_CLK Polarity = 0, Phase = 0,
from SPI0_CLK rising
17 20 27 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
17 20 27
Polarity = 1, Phase = 0,
from SPI0_CLK falling
17 20 27
Polarity = 1, Phase = 1,
from SPI0_CLK rising
17 20 27
14 toh(SPC_SOMI)S Output hold time, SPI0_SOMI valid after receive edge of SPI0_CLK Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5S-6 0.5S-16 0.5S-20 ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5S-6 0.5S-16 0.5S-20
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5S-6 0.5S-16 0.5S-20
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5S-6 0.5S-16 0.5S-20
15 tsu(SIMO_SPC)S Input Setup Time, SPI0_SIMO valid before receive edge of SPI0_CLK Polarity = 0, Phase = 0,
to SPI0_CLK falling
1.5 1.5 1.5 ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 0,
to SPI0_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.5 1.5 1.5
16 tih(SPC_SIMO)S Input Hold Time, SPI0_SIMO valid after receive edge of SPI0_CLK Polarity = 0, Phase = 0,
from SPI0_CLK falling
4 4 5 ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
4 4 5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
4 4 5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
4 4 5
P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)
This timing is limited by the timing shown or 3P, whichever is greater.
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by the CPU.

Table 6-72 Additional SPI0 Master Timings, 4-Pin Enable Option (5)(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
17 td(ENA_SPC)M Delay from slave assertion of SPI0_ENA active to first SPI0_CLK from master.(3) Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P+5 3P+5 3P+6 ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P+5 3P+5 3P+6
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
18 td(SPC_ENA)M Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer.(4) Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+5 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+5 P+5 P+6
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+5 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5 P+5 P+6
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_ENA assertion.
In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
These parameters are in addition to the general timings for SPI master modes (Table 6-70).

Table 6-73 Additional SPI0 Master Timings, 4-Pin Chip Select Option (7)(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
19 td(SCS_SPC)M Delay from SPI0_SCS active to first SPI0_CLK(3) (4) Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P-1 2P-2 2P-3 ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+2P-1 0.5M+2P-2 0.5M+2P-3
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P-1 2P-2 2P-3
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+2P-1 0.5M+2P-2 0.5M+2P-3
20 td(SPC_SCS)M Delay from final SPI0_CLK edge to master deasserting SPI0_SCS (5) (6) Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P-1 0.5M+P-2 0.5M+P-3 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P-1 P-2 P-3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P-1 0.5M+P-2 0.5M+P-3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P-1 P-2 P-3
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
These parameters are in addition to the general timings for SPI master modes (Table 6-70).

Table 6-74 Additional SPI0 Master Timings, 5-Pin Option (10)(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
18 td(SPC_ENA)M Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer.(3) Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+5 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+5 P+5 P+6
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+5 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5 P+5 P+6
20 td(SPC_SCS)M Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS (4) (5)
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P-2 0.5M+P-2 0.5M+P-3 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P-2 P-2 P-3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P-2 0.5M+P-2 0.5M+P-3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P-2 P-2 P-3
21 td(SCSL_ENAL)M Max delay for slave SPI to drive SPI0_ENA valid after master asserts SPI0_SCS to delay the master from beginning the next transfer, C2TDELAY+P C2TDELAY+P C2TDELAY+P ns
22 td(SCS_SPC)M Delay from SPI0_SCS active to first SPI0_CLK(6) (7) (8) Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P-2 2P-2 2P-3 ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+2P-2 0.5M+2P-2 0.5M+2P-3
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P-2 2P-2 2P-3
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+2P-2 0.5M+2P-2 0.5M+2P-3
23 td(ENA_SPC)M Delay from assertion of SPI0_ENA low to first SPI0_CLK edge.(9) Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P+5 3P+5 3P+6 ns
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P+5 3P+5 3P+6
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
In the case where the master SPI is ready with new data before SPI0_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
These parameters are in addition to the general timings for SPI master modes (Table 6-71).

Table 6-75 Additional SPI0 Slave Timings, 4-Pin Enable Option (3)(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
24 td(SPC_ENAH)S Delay from final SPI0_CLK edge to slave deasserting SPI0_ENA. Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5P-3 2.5P+17.5 1.5P-3 2.5P+20 1.5P-3 2.5P+27 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
– 0.5M+1.5P-3 – 0.5M+2.5P+17.5 – 0.5M+1.5P-3 – 0.5M+2.5P+20 – 0.5M+1.5P-3 – 0.5M+2.5P+27
Polarity = 1, Phase = 0,
from SPI0_CLK rising
1.5P-3 2.5P+17.5 1.5P-3 2.5P+20 1.5P-3 2.5P+27
Polarity = 1, Phase = 1,
from SPI0_CLK rising
– 0.5M+1.5P-3 – 0.5+2.5P+17.5 – 0.5M+1.5P-3 – 0.5+2.5P+20 – 0.5M+1.5P-3 – 0.5+2.5P+27
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
These parameters are in addition to the general timings for SPI slave modes (Table 6-71).

Table 6-76 Additional SPI0 Slave Timings, 4-Pin Chip Select Option (3)(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
25 td(SCSL_SPC)S Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. P + 1.5 P + 1.5 P + 1.5 ns
26 td(SPC_SCSH)S Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted. Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+4 0.5M+P+4 0.5M+P+5 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+4 P+4 P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+4 0.5M+P+4 0.5M+P+5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+4 P+4 P+5
27 tena(SCSL_SOMI)S Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid P+17.5 P+20 P+27 ns
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI P+17.5 P+20 P+27 ns
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
These parameters are in addition to the general timings for SPI slave modes (Table 6-71).

Table 6-77 Additional SPI0 Slave Timings, 5-Pin Option (4)(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
25 td(SCSL_SPC)S Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. P + 1.5 P + 1.5 P + 1.5 ns
26 td(SPC_SCSH)S Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted. Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+4 0.5M+P+4 0.5M+P+5 ns
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+4 P+4 P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+4 0.5M+P+4 0.5M+P+5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+4 P+4 P+5
27 tena(SCSL_SOMI)S Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid P+17.5 P+20 P+27 ns
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI P+17.5 P+20 P+27 ns
29 tena(SCSL_ENA)S Delay from master deasserting SPI0_SCS to slave driving SPI0_ENA valid 17.5 20 27 ns
30 tdis(SPC_ENA)S Delay from final clock receive edge on SPI0_CLK to slave 3-stating or driving high SPI0_ENA.(3) Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5P+17.5 2.5P+20 2.5P+27 ns
Polarity = 0, Phase = 1,
from SPI0_CLK rising
2.5P+17.5 2.5P+20 2.5P+27
Polarity = 1, Phase = 0,
from SPI0_CLK rising
2.5P+17.5 2.5P+20 2.5P+27
Polarity = 1, Phase = 1,
from SPI0_CLK falling
2.5P+17.5 2.5P+20 2.5P+27
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
These parameters are in addition to the general timings for SPI slave modes (Table 6-71).

Table 6-78 General Timing Requirements for SPI1 Master Modes(1)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tc(SPC)M Cycle Time, SPI1_CLK, All Master Modes 20(2) 256P 30(2) 256P 40(2) 256P ns
2 tw(SPCH)M Pulse Width High, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns
3 tw(SPCL)M Pulse Width Low, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns
4 td(SIMO_SPC)M Delay, initial data bit valid on SPI1_SIMO to initial edge on SPI1_CLK(3) Polarity = 0, Phase = 0,
to SPI1_CLK rising
5 5 6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
-0.5M+5 -0.5M+5 -0.5M+6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
5 5 6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
-0.5M+5 -0.5M+5 -0.5M+6
5 td(SPC_SIMO)M Delay, subsequent bits valid on SPI1_SIMO after transmit edge of SPI1_CLK Polarity = 0, Phase = 0,
from SPI1_CLK rising
5 5 6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
5 5 6
Polarity = 1, Phase = 0,
from SPI1_CLK falling
5 5 6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
5 5 6
6 toh(SPC_SIMO)M Output hold time, SPI1_SIMO valid after receive edge of SPI1_CLK Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M-3 0.5M-3 0.5M-3 ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5M-3 0.5M-3 0.5M-3
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M-3 0.5M-3 0.5M-3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5M-3 0.5M-3 0.5M-3
7 tsu(SOMI_SPC)M Input Setup Time, SPI1_SOMI valid before receive edge of SPI1_CLK Polarity = 0, Phase = 0,
to SPI1_CLK falling
1.5 1.5 1.5 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 0,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
1.5 1.5 1.5
8 tih(SPC_SOMI)M Input Hold Time, SPI1_SOMI valid after receive edge of SPI1_CLK Polarity = 0, Phase = 0,
from SPI1_CLK falling
4 5 6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 1,
from SPI1_CLK falling
4 5 6
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
This timing is limited by the timing shown or 3P, whichever is greater.
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.

Table 6-79 General Timing Requirements for SPI1 Slave Modes(1)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
9 tc(SPC)S Cycle Time, SPI1_CLK, All Slave Modes 40(2) 50(2) 60(2) ns
10 tw(SPCH)S Pulse Width High, SPI1_CLK, All Slave Modes 18 22 27 ns
11 tw(SPCL)S Pulse Width Low, SPI1_CLK, All Slave Modes 18 22 27 ns
12 tsu(SOMI_SPC)S Setup time, transmit data written to SPI before initial clock edge from
master.(3)(4)
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P 2P 2P ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
2P 2P 2P
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P 2P 2P
Polarity = 1, Phase = 1,
to SPI1_CLK falling
2P 2P 2P
13 td(SPC_SOMI)S Delay, subsequent bits valid on SPI1_SOMI after transmit edge of SPI1_CLK Polarity = 0, Phase = 0,
from SPI1_CLK rising
15 17 19 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
15 17 19
Polarity = 1, Phase = 0,
from SPI1_CLK falling
15 17 19
Polarity = 1, Phase = 1,
from SPI1_CLK rising
15 17 19
14 toh(SPC_SOMI)S Output hold time, SPI1_SOMI valid after receive edge of SPI1_CLK Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5S-4 0.5S-10 0.5S-12 ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5S-4 0.5S-10 0.5S-12
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5S-4 0.5S-10 0.5S-12
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5S-4 0.5S-10 0.5S-12
15 tsu(SIMO_SPC)S Input Setup Time, SPI1_SIMO valid before receive edge of SPI1_CLK Polarity = 0, Phase = 0,
to SPI1_CLK falling
1.5 1.5 1.5 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 0,
to SPI1_CLK rising
1.5 1.5 1.5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
1.5 1.5 1.5
16 tih(SPC_SIMO)S Input Hold Time, SPI1_SIMO valid after receive edge of SPI1_CLK Polarity = 0, Phase = 0,
from SPI1_CLK falling
4 5 6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
4 5 6
Polarity = 1, Phase = 1,
from SPI1_CLK falling
4 5 6
P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)
This timing is limited by the timing shown or 3P, whichever is greater.
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by the CPU.

Table 6-80 Additional(5) SPI1 Master Timings, 4-Pin Enable Option(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
17 td(EN A_SPC)M Delay from slave assertion of SPI1_ENA active to first SPI1_CLK from master.(3) Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P+5 3P+5 3P+6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P+5 3P+5 3P+6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
18 td(SPC_ENA)M Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer.(4) Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+5 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+5 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+5 P+5 P+6
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_ENA assertion.
In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
These parameters are in addition to the general timings for SPI master modes (Table 6-78).

Table 6-81 Additional(7) SPI1 Master Timings, 4-Pin Chip Select Option(1) (2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
19 td(SCS_SPC)M Delay from SPI1_SCS active to first SPI1_CLK(3) (4) Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P-1 2P-5 2P-6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P-1 2P-5 2P-6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
20 td(SPC_SCS)M Delay from final SPI1_CLK edge to master deasserting SPI1_SCS (5) (6) Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P-1 0.5M+P-5 0.5M+P-6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P-1 P-5 P-6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P-1 0.5M+P-5 0.5M+P-6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P-1 P-5 P-6
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
These parameters are in addition to the general timings for SPI master modes (Table 6-78).

Table 6-82 Additional(10) SPI1 Master Timings, 5-Pin Option(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
18 td(SPC_ENA)M Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer.(3) Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+5 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+5 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+5 P+5 P+6
20 td(SPC_SCS)M Delay from final SPI1_CLK edge to
master deasserting SPI1_SCS (4)(5)
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P-1 0.5M+P-5 0.5M+P-6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P-1 P-5 P-6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P-1 0.5M+P-5 0.5M+P-6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P-1 P-5 P-6
21 td(SCSL_ENAL)M Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to delay the
master from beginning the next transfer,
C2TDELAY+P C2TDELAY+P C2TDELAY+P ns
22 td(SCS_SPC)M Delay from SPI1_SCS active to first SPI1_CLK(6)(7)(8) Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P-1 2P-5 2P-6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P-1 2P-5 2P-6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
23 td(ENA_SPC)M Delay from assertion of SPI1_ENA low to first SPI1_CLK edge.(9) Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P+5 3P+5 3P+6 ns
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P+5 3P+5 3P+6
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
In the case where the master SPI is ready with new data before SPI1_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
These parameters are in addition to the general timings for SPI master modes (Table 6-79).

Table 6-83 Additional(3) SPI1 Slave Timings, 4-Pin Enable Option(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
24 td(SPC_ENAH)S Delay from final SPI1_CLK edge to slave deasserting SPI1_ENA. Polarity = 0, Phase = 0,
from SPI1_CLK falling
1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
–0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19
Polarity = 1, Phase = 0,
from SPI1_CLK rising
1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19
Polarity = 1, Phase = 1,
from SPI1_CLK rising
–0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
These parameters are in addition to the general timings for SPI slave modes (Table 6-79).

Table 6-84 Additional(3) SPI1 Slave Timings, 4-Pin Chip Select Option(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
25 td(SCSL_SPC)S Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. P+1.5 P+1.5 P+1.5 ns
26 td(SPC_SCSH)S Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+4 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+4 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+4 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+4 P+5 P+6
27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
These parameters are in addition to the general timings for SPI slave modes (Table 6-79).

Table 6-85 Additional(4) SPI1 Slave Timings, 5-Pin Option(1)(2)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
25 td(SCSL_SPC)S Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. P+1.5 P+1.5 P+1.5 ns
26 td(SPC_SCSH)S Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+4 0.5M+P+5 0.5M+P+6 ns
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+4 P+5 P+6
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+4 0.5M+P+5 0.5M+P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+4 P+5 P+6
27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns
29 tena(SCSL_ENA)S Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid 15 17 19 ns
30 tdis(SPC_ENA)S Delay from final clock receive edge on SPI1_CLK to slave 3-stating or driving high SPI1_ENA.(3) Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5P+15 2.5P+17 2.5P+19 ns
Polarity = 0, Phase = 1,
from SPI1_CLK rising
2.5P+15 2.5P+17 2.5P+19
Polarity = 1, Phase = 0,
from SPI1_CLK rising
2.5P+15 2.5P+17 2.5P+19
Polarity = 1, Phase = 1,
from SPI1_CLK falling
2.5P+15 2.5P+17 2.5P+19
P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
These parameters are in addition to the general timings for SPI slave modes (Table 6-79).
OMAP-L138 spitim1a_prs279.gif Figure 6-38 SPI Timings—Master Mode
OMAP-L138 spitim2_prs279.gif Figure 6-39 SPI Timings—Slave Mode
OMAP-L138 spitim3_prs279.gif Figure 6-40 SPI Timings—Master Mode (4-Pin and 5-Pin)
OMAP-L138 spitim4_prs279.gif Figure 6-41 SPI Timings—Slave Mode (4-Pin and 5-Pin)

Inter-Integrated Circuit Serial Ports (I2C)

I2C Device-Specific Information

Each I2C port supports:

  • Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
  • Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
  • Noise Filter to Remove Noise 50 ns or less
  • Seven- and Ten-Bit Device Addressing Modes
  • Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
  • Events: DMA, Interrupt, or Polling
  • General-Purpose I/O Capability if not used as I2C

Figure 6-42 is block diagram of the device I2C Module.

OMAP-L138 bd_i2c_prs279.gif Figure 6-42 I2C Module Block Diagram

I2C Peripheral Registers Description(s)

Table 6-86 is the list of the I2C registers.

Table 6-86 Inter-Integrated Circuit (I2C) Registers

I2C0
BYTE ADDRESS
I2C1
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01C2 2000 0x01E2 8000 ICOAR I2C Own Address Register
0x01C2 2004 0x01E2 8004 ICIMR I2C Interrupt Mask Register
0x01C2 2008 0x01E2 8008 ICSTR I2C Interrupt Status Register
0x01C2 200C 0x01E2 800C ICCLKL I2C Clock Low-Time Divider Register
0x01C2 2010 0x01E2 8010 ICCLKH I2C Clock High-Time Divider Register
0x01C2 2014 0x01E2 8014 ICCNT I2C Data Count Register
0x01C2 2018 0x01E2 8018 ICDRR I2C Data Receive Register
0x01C2 201C 0x01E2 801C ICSAR I2C Slave Address Register
0x01C2 2020 0x01E2 8020 ICDXR I2C Data Transmit Register
0x01C2 2024 0x01E2 8024 ICMDR I2C Mode Register
0x01C2 2028 0x01E2 8028 ICIVR I2C Interrupt Vector Register
0x01C2 202C 0x01E2 802C ICEMDR I2C Extended Mode Register
0x01C2 2030 0x01E2 8030 ICPSC I2C Prescaler Register
0x01C2 2034 0x01E2 8034 REVID1 I2C Revision Identification Register 1
0x01C2 2038 0x01E2 8038 REVID2 I2C Revision Identification Register 2
0x01C2 2048 0x01E2 8048 ICPFUNC I2C Pin Function Register
0x01C2 204C 0x01E2 804C ICPDIR I2C Pin Direction Register
0x01C2 2050 0x01E2 8050 ICPDIN I2C Pin Data In Register
0x01C2 2054 0x01E2 8054 ICPDOUT I2C Pin Data Out Register
0x01C2 2058 0x01E2 8058 ICPDSET I2C Pin Data Set Register
0x01C2 205C 0x01E2 805C ICPDCLR I2C Pin Data Clear Register

I2C Electrical Data/Timing

Inter-Integrated Circuit (I2C) Timing

Table 6-87 and Table 6-88 assume testing over recommended operating conditions (see Figure 6-43 and Figure 6-44).

Table 6-87 Timing Requirements for I2C Input

NO. 1.3V, 1.2V, 1.1V, 1.0V UNIT
Standard Mode Fast Mode
MIN MAX MIN MAX
1 tc(SCL) Cycle time, I2Cx_SCL 10 2.5 μs
2 tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low 4.7 0.6 μs
3 th(SCLL-SDAL) Hold time, I2Cx_SCL low after I2Cx_SDA low 4 0.6 μs
4 tw(SCLL) Pulse duration, I2Cx_SCL low 4.7 1.3 μs
5 tw(SCLH) Pulse duration, I2Cx_SCL high 4 0.6 μs
6 tsu(SDA-SCLH) Setup time, I2Cx_SDA before I2Cx_SCL high 250 100 ns
7 th(SDA-SCLL) Hold time, I2Cx_SDA after I2Cx_SCL low 0 0 0.9 μs
8 tw(SDAH) Pulse duration, I2Cx_SDA high 4.7 1.3 μs
9 tr(SDA) Rise time, I2Cx_SDA 1000 20 + 0.1Cb 300 ns
10 tr(SCL) Rise time, I2Cx_SCL 1000 20 + 0.1Cb 300 ns
11 tf(SDA) Fall time, I2Cx_SDA 300 20 + 0.1Cb 300 ns
12 tf(SCL) Fall time, I2Cx_SCL 300 20 + 0.1Cb 300 ns
13 tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high 4 0.6 μs
14 tw(SP) Pulse duration, spike (must be suppressed) N/A 0 50 ns
15 Cb Capacitive load for each bus line 400 400 pF

Table 6-88 Switching Characteristics for I2C (1)

NO. PARAMETER 1.3V, 1.2V, 1.1V, 1.0V UNIT
Standard Mode Fast Mode
MIN MAX MIN MAX
16 tc(SCL) Cycle time, I2Cx_SCL 10 2.5 μs
17 tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low 4.7 0.6 μs
18 th(SDAL-SCLL) Hold time, I2Cx_SCL low after I2Cx_SDA low 4 0.6 μs
19 tw(SCLL) Pulse duration, I2Cx_SCL low 4.7 1.3 μs
20 tw(SCLH) Pulse duration, I2Cx_SCL high 4 0.6 μs
21 tsu(SDAV-SCLH) Setup time, I2Cx_SDA valid before I2Cx_SCL high 250 100 ns
22 th(SCLL-SDAV) Hold time, I2Cx_SDA valid after I2Cx_SCL low 0 0 0.9 μs
23 tw(SDAH) Pulse duration, I2Cx_SDA high 4.7 1.3 μs
28 tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high 4 0.6 μs
I2C must be configured correctly to meet the timings in Table 6-88.
OMAP-L138 td_i2c_rt_prs279.gif Figure 6-43 I2C Receive Timings
OMAP-L138 td_i2c_tt_prs279.gif Figure 6-44 I2C Transmit Timings

Universal Asynchronous Receiver/Transmitter (UART)

Each UART has the following features:

  • 16-byte storage space for both the transmitter and receiver FIFOs
  • 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
  • DMA signaling capability for both received and transmitted data
  • Programmable auto-rts and auto-cts for autoflow control
  • Programmable Baud Rate up to 12 MBaud
  • Programmable Oversampling Options of x13 and x16
  • Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
  • Prioritized interrupts
  • Programmable serial data formats
    • 5, 6, 7, or 8-bit characters
    • Even, odd, or no parity bit generation and detection
    • 1, 1.5, or 2 stop bit generation
  • False start bit detection
  • Line break generation and detection
  • Internal diagnostic capabilities
    • Loopback controls for communications link fault isolation
    • Break, parity, overrun, and framing error simulation
  • Modem control functions (CTS, RTS)

The UART registers are listed in Section 6.19.1

UART Peripheral Registers Description(s)

Table 6-89 is the list of UART registers.

Table 6-89 UART Registers

UART0
BYTE ADDRESS
UART1
BYTE ADDRESS
UART2
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01C4 2000 0x01D0 C000 0x01D0 D000 RBR Receiver Buffer Register (read only)
0x01C4 2000 0x01D0 C000 0x01D0 D000 THR Transmitter Holding Register (write only)
0x01C4 2004 0x01D0 C004 0x01D0 D004 IER Interrupt Enable Register
0x01C4 2008 0x01D0 C008 0x01D0 D008 IIR Interrupt Identification Register (read only)
0x01C4 2008 0x01D0 C008 0x01D0 D008 FCR FIFO Control Register (write only)
0x01C4 200C 0x01D0 C00C 0x01D0 D00C LCR Line Control Register
0x01C4 2010 0x01D0 C010 0x01D0 D010 MCR Modem Control Register
0x01C4 2014 0x01D0 C014 0x01D0 D014 LSR Line Status Register
0x01C4 2018 0x01D0 C018 0x01D0 D018 MSR Modem Status Register
0x01C4 201C 0x01D0 C01C 0x01D0 D01C SCR Scratchpad Register
0x01C4 2020 0x01D0 C020 0x01D0 D020 DLL Divisor LSB Latch
0x01C4 2024 0x01D0 C024 0x01D0 D024 DLH Divisor MSB Latch
0x01C4 2028 0x01D0 C028 0x01D0 D028 REVID1 Revision Identification Register 1
0x01C4 2030 0x01D0 C030 0x01D0 D030 PWREMU_MGMT Power and Emulation Management Register
0x01C4 2034 0x01D0 C034 0x01D0 D034 MDR Mode Definition Register

UART Electrical Data/Timing

Table 6-90 Timing Requirements for UART Receive(1) (see Figure 6-45)

NO. 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
4 tw(URXDB) Pulse duration, receive data bit (RXDn) 0.96U 1.05U ns
5 tw(URXSB) Pulse duration, receive start bit 0.96U 1.05U ns
U = UART baud time = 1/programmed baud rate.

Table 6-91 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-45)

NO. PARAMETER 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
1 f(baud) Maximum programmable baud rate D/E (2) (3) MBaud (4)
2 tw(UTXDB) Pulse duration, transmit data bit (TXDn) U - 2 U + 2 ns
3 tw(UTXSB) Pulse duration, transmit start bit U - 2 U + 2 ns
U = UART baud time = 1/programmed baud rate.
D = UART input clock in MHz.
For UART0, the UART input clock is SYSCLK2.
For UART1 or UART2, the UART input clock is ASYNC3 (either PLL0_SYCLK2 or PLL1_SYSCLK2).
E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).
Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF/DDR loading, system frequency, etc.
OMAP-L138 td_uart_prs271.gif Figure 6-45 UART Transmit/Receive Timing

Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]

The USB2.0 peripheral supports the following features:

  • USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
  • USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
  • All transfer modes (control, bulk, interrupt, and isochronous)
  • 4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
  • FIFO RAM
    • 4K endpoint
    • Programmable size
  • Integrated USB 2.0 High Speed PHY
  • Connects to a standard Charge Pump for VBUS 5 V generation
  • RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB

Important Notice: The USB0 controller module clock (PLL0_SYSCLK2) must be greater than 30 MHz for proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data throughput reduction.

Table 6-92 is the list of USB OTG registers.

Table 6-92 Universal Serial Bus OTG (USB0) Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E0 0000 REVID Revision Register
0x01E0 0004 CTRLR Control Register
0x01E0 0008 STATR Status Register
0x01E0 000C EMUR Emulation Register
0x01E0 0010 MODE Mode Register
0x01E0 0014 AUTOREQ Autorequest Register
0x01E0 0018 SRPFIXTIME SRP Fix Time Register
0x01E0 001C TEARDOWN Teardown Register
0x01E0 0020 INTSRCR USB Interrupt Source Register
0x01E0 0024 INTSETR USB Interrupt Source Set Register
0x01E0 0028 INTCLRR USB Interrupt Source Clear Register
0x01E0 002C INTMSKR USB Interrupt Mask Register
0x01E0 0030 INTMSKSETR USB Interrupt Mask Set Register
0x01E0 0034 INTMSKCLRR USB Interrupt Mask Clear Register
0x01E0 0038 INTMASKEDR USB Interrupt Source Masked Register
0x01E0 003C EOIR USB End of Interrupt Register
0x01E0 0040 - Reserved
0x01E0 0050 GENRNDISSZ1 Generic RNDIS Size EP1
0x01E0 0054 GENRNDISSZ2 Generic RNDIS Size EP2
0x01E0 0058 GENRNDISSZ3 Generic RNDIS Size EP3
0x01E0 005C GENRNDISSZ4 Generic RNDIS Size EP4
0x01E0 0400 FADDR Function Address Register
0x01E0 0401 POWER Power Management Register
0x01E0 0402 INTRTX Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
0x01E0 0404 INTRRX Interrupt Register for Receive Endpoints 1 to 4
0x01E0 0406 INTRTXE Interrupt enable register for INTRTX
0x01E0 0408 INTRRXE Interrupt Enable Register for INTRRX
0x01E0 040A INTRUSB Interrupt Register for Common USB Interrupts
0x01E0 040B INTRUSBE Interrupt Enable Register for INTRUSB
0x01E0 040C FRAME Frame Number Register
0x01E0 040E INDEX Index Register for Selecting the Endpoint Status and Control Registers
0x01E0 040F TESTMODE Register to Enable the USB 2.0 Test Modes
Indexed Registers
These registers operate on the endpoint selected by the INDEX register
0x01E0 0410 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
(Index register set to select Endpoints 1-4 only)
0x01E0 0412 PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral Mode.
(Index register set to select Endpoint 0)
HOST_CSR0 Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint.
(Index register set to select Endpoints 1-4)
HOST_TXCSR Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
(Index register set to select Endpoints 1-4 only)
0x01E0 0416 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint.
(Index register set to select Endpoints 1-4)
HOST_RXCSR Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0418 COUNT0 Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
0x01E0 041A HOST_TYPE0 Defines the speed of Endpoint 0
HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041B HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041F CONFIGDATA Returns details of core configuration. (Index register set to select Endpoint 0)
FIFO
0x01E0 0420 FIFO0 Transmit and Receive FIFO Register for Endpoint 0
0x01E0 0424 FIFO1 Transmit and Receive FIFO Register for Endpoint 1
0x01E0 0428 FIFO2 Transmit and Receive FIFO Register for Endpoint 2
0x01E0 042C FIFO3 Transmit and Receive FIFO Register for Endpoint 3
0x01E0 0430 FIFO4 Transmit and Receive FIFO Register for Endpoint 4
OTG Device Control
0x01E0 0460 DEVCTL Device Control Register
Dynamic FIFO Control
0x01E0 0462 TXFIFOSZ Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0463 RXFIFOSZ Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0464 TXFIFOADDR Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 0466 RXFIFOADDR Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 046C HWVERS Hardware Version Register
Target Endpoint 0 Control Registers, Valid Only in Host Mode
0x01E0 0480 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 0482 TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0483 TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0484 RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 0486 RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0487 RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 1 Control Registers, Valid Only in Host Mode
0x01E0 0488 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 048A TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048B TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048C RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 048E RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048F RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 2 Control Registers, Valid Only in Host Mode
0x01E0 0490 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 0492 TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0493 TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0494 RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 0496 RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0497 RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 3 Control Registers, Valid Only in Host Mode
0x01E0 0498 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 049A TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049B TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049C RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 049E RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049F RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 4 Control Registers, Valid Only in Host Mode
0x01E0 04A0 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 04A2 TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A3 TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A4 RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 04A6 RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A7 RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Control and Status Register for Endpoint 0
0x01E0 0502 PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral Mode
HOST_CSR0 Control Status Register for Endpoint 0 in Host Mode
0x01E0 0508 COUNT0 Number of Received Bytes in Endpoint 0 FIFO
0x01E0 050A HOST_TYPE0 Defines the Speed of Endpoint 0
0x01E0 050B HOST_NAKLIMIT0 Sets the NAK Response Timeout on Endpoint 0
0x01E0 050F CONFIGDATA Returns details of core configuration.
Control and Status Register for Endpoint 1
0x01E0 0510 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0512 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0514 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0516 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0518 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 051A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 051B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 051C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 051D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 2
0x01E0 0520 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0522 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0524 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0526 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0528 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 052A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 052B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 052C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 052D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 3
0x01E0 0530 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0532 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0534 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0536 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0538 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 053A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 053B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 053C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 053D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 4
0x01E0 0540 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0542 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0544 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0546 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0548 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 054A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 054B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 054C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 054D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
DMA Registers
0x01E0 1000 DMAREVID DMA Revision Register
0x01E0 1004 TDFDQ DMA Teardown Free Descriptor Queue Control Register
0x01E0 1008 DMAEMU DMA Emulation Control Register
0x01E0 1800 TXGCR[0] Transmit Channel 0 Global Configuration Register
0x01E0 1808 RXGCR[0] Receive Channel 0 Global Configuration Register
0x01E0 180C RXHPCRA[0] Receive Channel 0 Host Packet Configuration Register A
0x01E0 1810 RXHPCRB[0] Receive Channel 0 Host Packet Configuration Register B
0x01E0 1820 TXGCR[1] Transmit Channel 1 Global Configuration Register
0x01E0 1828 RXGCR[1] Receive Channel 1 Global Configuration Register
0x01E0 182C RXHPCRA[1] Receive Channel 1 Host Packet Configuration Register A
0x01E0 1830 RXHPCRB[1] Receive Channel 1 Host Packet Configuration Register B
0x01E0 1840 TXGCR[2] Transmit Channel 2 Global Configuration Register
0x01E0 1848 RXGCR[2] Receive Channel 2 Global Configuration Register
0x01E0 184C RXHPCRA[2] Receive Channel 2 Host Packet Configuration Register A
0x01E0 1850 RXHPCRB[2] Receive Channel 2 Host Packet Configuration Register B
0x01E0 1860 TXGCR[3] Transmit Channel 3 Global Configuration Register
0x01E0 1868 RXGCR[3] Receive Channel 3 Global Configuration Register
0x01E0 186C RXHPCRA[3] Receive Channel 3 Host Packet Configuration Register A
0x01E0 1870 RXHPCRB[3] Receive Channel 3 Host Packet Configuration Register B
0x01E0 2000 DMA_SCHED_CTRL DMA Scheduler Control Register
0x01E0 2800 WORD[0] DMA Scheduler Table Word 0
0x01E0 2804 WORD[1] DMA Scheduler Table Word 1
. . . . . . . . .
0x01E0 28FC WORD[63] DMA Scheduler Table Word 63
Queue Manager Registers
0x01E0 4000 QMGRREVID Queue Manager Revision Register
0x01E0 4008 DIVERSION Queue Diversion Register
0x01E0 4020 FDBSC0 Free Descriptor/Buffer Starvation Count Register 0
0x01E0 4024 FDBSC1 Free Descriptor/Buffer Starvation Count Register 1
0x01E0 4028 FDBSC2 Free Descriptor/Buffer Starvation Count Register 2
0x01E0 402C FDBSC3 Free Descriptor/Buffer Starvation Count Register 3
0x01E0 4080 LRAM0BASE Linking RAM Region 0 Base Address Register
0x01E0 4084 LRAM0SIZE Linking RAM Region 0 Size Register
0x01E0 4088 LRAM1BASE Linking RAM Region 1 Base Address Register
0x01E0 4090 PEND0 Queue Pending Register 0
0x01E0 4094 PEND1 Queue Pending Register 1
0x01E0 5000 QMEMRBASE[0] Memory Region 0 Base Address Register
0x01E0 5004 QMEMRCTRL[0] Memory Region 0 Control Register
0x01E0 5010 QMEMRBASE[1] Memory Region 1 Base Address Register
0x01E0 5014 QMEMRCTRL[1] Memory Region 1 Control Register
. . . . . . . . .
0x01E0 50F0 QMEMRBASE[15] Memory Region 15 Base Address Register
0x01E0 50F4 QMEMRCTRL[15] Memory Region 15 Control Register
0x01E0 600C CTRLD[0] Queue Manager Queue 0 Control Register D
0x01E0 601C CTRLD[1] Queue Manager Queue 1 Control Register D
. . . . . . . . .
0x01E0 63FC CTRLD[63] Queue Manager Queue 63 Status Register D
0x01E0 6800 QSTATA[0] Queue Manager Queue 0 Status Register A
0x01E0 6804 QSTATB[0] Queue Manager Queue 0 Status Register B
0x01E0 6808 QSTATC[0] Queue Manager Queue 0 Status Register C
0x01E0 6810 QSTATA[1] Queue Manager Queue 1 Status Register A
0x01E0 6814 QSTATB[1] Queue Manager Queue 1 Status Register B
0x01E0 6818 QSTATC[1] Queue Manager Queue 1 Status Register C
. . . . . . . . .
0x01E0 6BF0 QSTATA[63] Queue Manager Queue 63 Status Register A
0x01E0 6BF4 QSTATB[63] Queue Manager Queue 63 Status Register B
0x01E0 6BF8 QSTATC[63] Queue Manager Queue 63 Status Register C

USB0 [USB2.0] Electrical Data/Timing

The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz, 20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50 ppm (maximum).

Table 6-93 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see Figure 6-46)

NO. PARAMETER 1.3V, 1.2V, 1.1V, 1.0V UNIT
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
MIN MAX MIN MAX MIN MAX
1 tr(D) Rise time, USB_DP and USB_DM signals(1) 75 300 4 20 0.5 ns
2 tf(D) Fall time, USB_DP and USB_DM signals(1) 75 300 4 20 0.5 ns
3 trfM Rise/Fall time, matching(2) 80 120 90 111 %
4 VCRS Output signal cross-over voltage(1) 1.3 2 1.3 2 V
5 tjr(source)NT Source (Host) Driver jitter, next transition 2 2 (4) ns
tjr(FUNC)NT Function Driver jitter, next transition 25 2 (4) ns
6 tjr(source)PT Source (Host) Driver jitter, paired transition(3) 1 1 (4) ns
tjr(FUNC)PT Function Driver jitter, paired transition 10 1 (4) ns
7 tw(EOPT) Pulse duration, EOP transmitter 1250 1500 160 175 ns
8 tw(EOPR) Pulse duration, EOP receiver 670 82 ns
9 t(DRATE) Data Rate 1.5 12 480 Mb/s
10 ZDRV Driver Output Resistance 40.5 49.5 40.5 49.5 Ω
11 ZINP Receiver Input Impedance 100k 100k - - Ω
Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
tjr = tpx(1) - tpx(0)
For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
OMAP-L138 td_usbxrcv_prs271.gif Figure 6-46 USB2.0 Integrated Transceiver Interface Timing

Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]

All the USB interfaces for this device are compliant with Universal Serial Bus Specifications, Revision 1.1.

Table 6-94 is the list of USB Host Controller registers.

Table 6-94 USB Host Controller Registers

USB1
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01E2 5000 HCREVISION OHCI Revision Number Register
0x01E2 5004 HCCONTROL HC Operating Mode Register
0x01E2 5008 HCCOMMANDSTATUS HC Command and Status Register
0x01E2 500C HCINTERRUPTSTATUS HC Interrupt and Status Register
0x01E2 5010 HCINTERRUPTENABLE HC Interrupt Enable Register
0x01E2 5014 HCINTERRUPTDISABLE HC Interrupt Disable Register
0x01E2 5018 HCHCCA HC HCAA Address Register(1)
0x01E2 501C HCPERIODCURRENTED HC Current Periodic Register(1)
0x01E2 5020 HCCONTROLHEADED HC Head Control Register(1)
0x01E2 5024 HCCONTROLCURRENTED HC Current Control Register(1)
0x01E2 5028 HCBULKHEADED HC Head Bulk Register(1)
0x01E2 502C HCBULKCURRENTED HC Current Bulk Register(1)
0x01E2 5030 HCDONEHEAD HC Head Done Register(1)
0x01E2 5034 HCFMINTERVAL HC Frame Interval Register
0x01E2 5038 HCFMREMAINING HC Frame Remaining Register
0x01E2 503C HCFMNUMBER HC Frame Number Register
0x01E2 5040 HCPERIODICSTART HC Periodic Start Register
0x01E2 5044 HCLSTHRESHOLD HC Low-Speed Threshold Register
0x01E2 5048 HCRHDESCRIPTORA HC Root Hub A Register
0x01E2 504C HCRHDESCRIPTORB HC Root Hub B Register
0x01E2 5050 HCRHSTATUS HC Root Hub Status Register
0x01E2 5054 HCRHPORTSTATUS1 HC Port 1 Status and Control Register(2)
0x01E2 5058 HCRHPORTSTATUS2 HC Port 2 Status and Control Register(3)
Restrictions apply to the physical addresses used in these registers.
Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP).
Although the controller implements two ports, the second port cannot be used.

Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1 [USB1.1]

NO. PARAMETER 1.3V, 1.2V, 1.1V, 1.0V UNIT
LOW SPEED FULL SPEED
MIN MAX MAX MAX
U1 tr Rise time, USB.DP and USB.DM signals(1) 75(1) 300(1) 4(1) 20(1) ns
U2 tf Fall time, USB.DP and USB.DM signals(1) 75(1) 300(1) 4(1) 20(1) ns
U3 tRFM Rise/Fall time matching(2) 80(2) 120(2) 90(2) 110(2) %
U4 VCRS Output signal cross-over voltage(1) 1.3(1) 2(1) 1.3(1) 2(1) V
U5 tj Differential propagation jitter(3) -25(3) 25(3) -2(3) 2(3) ns
U6 fop Operating frequency(4) 1.5 12 MHz
Low Speed: CL = 200 pF. High Speed: CL = 50pF
tRFM =( tr/tf ) x 100
t jr = t px(1) - tpx(0)
fop = 1/tper

Ethernet Media Access Controller (EMAC)

The Ethernet Media Access Controller (EMAC) provides an efficient interface between device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts.

EMAC Peripheral Register Description(s)

Table 6-96 Ethernet Media Access Controller (EMAC) Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 3000 TXREV Transmit Revision Register
0x01E2 3004 TXCONTROL Transmit Control Register
0x01E2 3008 TXTEARDOWN Transmit Teardown Register
0x01E2 3010 RXREV Receive Revision Register
0x01E2 3014 RXCONTROL Receive Control Register
0x01E2 3018 RXTEARDOWN Receive Teardown Register
0x01E2 3080 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register
0x01E2 3084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register
0x01E2 3088 TXINTMASKSET Transmit Interrupt Mask Set Register
0x01E2 308C TXINTMASKCLEAR Transmit Interrupt Clear Register
0x01E2 3090 MACINVECTOR MAC Input Vector Register
0x01E2 3094 MACEOIVECTOR MAC End Of Interrupt Vector Register
0x01E2 30A0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register
0x01E2 30A4 RXINTSTATMASKED Receive Interrupt Status (Masked) Register
0x01E2 30A8 RXINTMASKSET Receive Interrupt Mask Set Register
0x01E2 30AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register
0x01E2 30B0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register
0x01E2 30B4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register
0x01E2 30B8 MACINTMASKSET MAC Interrupt Mask Set Register
0x01E2 30BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register
0x01E2 3100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register
0x01E2 3104 RXUNICASTSET Receive Unicast Enable Set Register
0x01E2 3108 RXUNICASTCLEAR Receive Unicast Clear Register
0x01E2 310C RXMAXLEN Receive Maximum Length Register
0x01E2 3110 RXBUFFEROFFSET Receive Buffer Offset Register
0x01E2 3114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
0x01E2 3120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register
0x01E2 3124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register
0x01E2 3128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register
0x01E2 312C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register
0x01E2 3130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register
0x01E2 3134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register
0x01E2 3138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register
0x01E2 313C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register
0x01E2 3140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register
0x01E2 3144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register
0x01E2 3148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register
0x01E2 314C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register
0x01E2 3150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register
0x01E2 3154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register
0x01E2 3158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register
0x01E2 315C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register
0x01E2 3160 MACCONTROL MAC Control Register
0x01E2 3164 MACSTATUS MAC Status Register
0x01E2 3168 EMCONTROL Emulation Control Register
0x01E2 316C FIFOCONTROL FIFO Control Register
0x01E2 3170 MACCONFIG MAC Configuration Register
0x01E2 3174 SOFTRESET Soft Reset Register
0x01E2 31D0 MACSRCADDRLO MAC Source Address Low Bytes Register
0x01E2 31D4 MACSRCADDRHI MAC Source Address High Bytes Register
0x01E2 31D8 MACHASH1 MAC Hash Address Register 1
0x01E2 31DC MACHASH2 MAC Hash Address Register 2
0x01E2 31E0 BOFFTEST Back Off Test Register
0x01E2 31E4 TPACETEST Transmit Pacing Algorithm Test Register
0x01E2 31E8 RXPAUSE Receive Pause Timer Register
0x01E2 31EC TXPAUSE Transmit Pause Timer Register
0x01E2 3200 - 0x01E2 32FC (see Table 6-97) EMAC Statistics Registers
0x01E2 3500 MACADDRLO MAC Address Low Bytes Register, Used in Receive Address Matching
0x01E2 3504 MACADDRHI MAC Address High Bytes Register, Used in Receive Address Matching
0x01E2 3508 MACINDEX MAC Index Register
0x01E2 3600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register
0x01E2 360C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register
0x01E2 361C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register
0x01E2 362C RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register
0x01E2 363C RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3640 TX0CP Transmit Channel 0 Completion Pointer Register
0x01E2 3644 TX1CP Transmit Channel 1 Completion Pointer Register
0x01E2 3648 TX2CP Transmit Channel 2 Completion Pointer Register
0x01E2 364C TX3CP Transmit Channel 3 Completion Pointer Register
0x01E2 3650 TX4CP Transmit Channel 4 Completion Pointer Register
0x01E2 3654 TX5CP Transmit Channel 5 Completion Pointer Register
0x01E2 3658 TX6CP Transmit Channel 6 Completion Pointer Register
0x01E2 365C TX7CP Transmit Channel 7 Completion Pointer Register
0x01E2 3660 RX0CP Receive Channel 0 Completion Pointer Register
0x01E2 3664 RX1CP Receive Channel 1 Completion Pointer Register
0x01E2 3668 RX2CP Receive Channel 2 Completion Pointer Register
0x01E2 366C RX3CP Receive Channel 3 Completion Pointer Register
0x01E2 3670 RX4CP Receive Channel 4 Completion Pointer Register
0x01E2 3674 RX5CP Receive Channel 5 Completion Pointer Register
0x01E2 3678 RX6CP Receive Channel 6 Completion Pointer Register
0x01E2 367C RX7CP Receive Channel 7 Completion Pointer Register

Table 6-97 EMAC Statistics Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 3200 RXGOODFRAMES Good Receive Frames Register
0x01E2 3204 RXBCASTFRAMES Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3208 RXMCASTFRAMES Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 320C RXPAUSEFRAMES Pause Receive Frames Register
0x01E2 3210 RXCRCERRORS Receive CRC Errors Register
(Total number of frames received with CRC errors)
0x01E2 3214 RXALIGNCODEERRORS Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
0x01E2 3218 RXOVERSIZED Receive Oversized Frames Register
(Total number of oversized frames received)
0x01E2 321C RXJABBER Receive Jabber Frames Register
(Total number of jabber frames received)
0x01E2 3220 RXUNDERSIZED Receive Undersized Frames Register
(Total number of undersized frames received)
0x01E2 3224 RXFRAGMENTS Receive Frame Fragments Register
0x01E2 3228 RXFILTERED Filtered Receive Frames Register
0x01E2 322C RXQOSFILTERED Received QOS Filtered Frames Register
0x01E2 3230 RXOCTETS Receive Octet Frames Register
(Total number of received bytes in good frames)
0x01E2 3234 TXGOODFRAMES Good Transmit Frames Register
(Total number of good frames transmitted)
0x01E2 3238 TXBCASTFRAMES Broadcast Transmit Frames Register
0x01E2 323C TXMCASTFRAMES Multicast Transmit Frames Register
0x01E2 3240 TXPAUSEFRAMES Pause Transmit Frames Register
0x01E2 3244 TXDEFERRED Deferred Transmit Frames Register
0x01E2 3248 TXCOLLISION Transmit Collision Frames Register
0x01E2 324C TXSINGLECOLL Transmit Single Collision Frames Register
0x01E2 3250 TXMULTICOLL Transmit Multiple Collision Frames Register
0x01E2 3254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register
0x01E2 3258 TXLATECOLL Transmit Late Collision Frames Register
0x01E2 325C TXUNDERRUN Transmit Underrun Error Register
0x01E2 3260 TXCARRIERSENSE Transmit Carrier Sense Errors Register
0x01E2 3264 TXOCTETS Transmit Octet Frames Register
0x01E2 3268 FRAME64 Transmit and Receive 64 Octet Frames Register
0x01E2 326C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register
0x01E2 3270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register
0x01E2 3274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register
0x01E2 3278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register
0x01E2 327C FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register
0x01E2 3280 NETOCTETS Network Octet Frames Register
0x01E2 3284 RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register
0x01E2 3288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register
0x01E2 328C RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns Register

Table 6-98 EMAC Control Module Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 2000 REV EMAC Control Module Revision Register
0x01E2 2004 SOFTRESET EMAC Control Module Software Reset Register
0x01E2 200C INTCONTROL EMAC Control Module Interrupt Control Register
0x01E2 2010 C0RXTHRESHEN EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
0x01E2 2014 C0RXEN EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
0x01E2 2018 C0TXEN EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
0x01E2 201C C0MISCEN EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
0x01E2 2020 C1RXTHRESHEN EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
0x01E2 2024 C1RXEN EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
0x01E2 2028 C1TXEN EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
0x01E2 202C C1MISCEN EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
0x01E2 2030 C2RXTHRESHEN EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
0x01E2 2034 C2RXEN EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
0x01E2 2038 C2TXEN EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
0x01E2 203C C2MISCEN EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
0x01E2 2040 C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
0x01E2 2044 C0RXSTAT EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
0x01E2 2048 C0TXSTAT EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
0x01E2 204C C0MISCSTAT EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
0x01E2 2050 C1RXTHRESHSTAT EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
0x01E2 2054 C1RXSTAT EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
0x01E2 2058 C1TXSTAT EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
0x01E2 205C C1MISCSTAT EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
0x01E2 2060 C2RXTHRESHSTAT EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
0x01E2 2064 C2RXSTAT EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
0x01E2 2068 C2TXSTAT EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
0x01E2 206C C2MISCSTAT EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
0x01E2 2070 C0RXIMAX EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
0x01E2 2074 C0TXIMAX EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
0x01E2 2078 C1RXIMAX EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
0x01E2 207C C1TXIMAX EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
0x01E2 2080 C2RXIMAX EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
0x01E2 2084 C2TXIMAX EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register

Table 6-99 EMAC Control Module RAM

BYTE ADDRESS DESCRIPTION
0x01E2 0000 - 0x01E2 1FFF EMAC Local Buffer Descriptor Memory

EMAC Electrical Data/Timing

Table 6-100 Timing Requirements for MII_RXCLK (see Figure 6-47)

NO. 1.3V, 1.2V, 1.1V 1.0V UNIT
10 Mbps 100 Mbps 10 Mbps
MIN MAX MIN MAX MIN MAX
1 tc(MII_RXCLK) Cycle time, MII_RXCLK 400 40 400 ns
2 tw(MII_RXCLKH) Pulse duration, MII_RXCLK high 140 14 140 ns
3 tw(MII_RXCLKL) Pulse duration, MII_RXCLK low 140 14 140 ns
OMAP-L138 td_mrclk_prs345.gif Figure 6-47 MII_RXCLK Timing (EMAC - Receive)

Table 6-101 Timing Requirements for MII_TXCLK (see Figure 6-48)

NO. 1.3V, 1.2V, 1.1V 1.0V UNIT
10 Mbps 100 Mbps 10 Mbps
MIN MAX MIN MAX MIN MAX
1 tc(MII_TXCLK) Cycle time, MII_TXCLK 400 40 400 ns
2 tw(MII_TXCLKH) Pulse duration, MII_TXCLK high 140 14 140 ns
3 tw(MII_TXCLKL) Pulse duration, MII_TXCLK low 140 14 140 ns
OMAP-L138 td_mtclk_prs345.gif Figure 6-48 MII_TXCLK Timing (EMAC - Transmit)

Table 6-102 Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-49)

NO. 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
1 tsu(MRXD-MII_RXCLKH) Setup time, receive selected signals valid before MII_RXCLK high 8 ns
2 th(MII_RXCLKH-MRXD) Hold time, receive selected signals valid after MII_RXCLK high 8 ns
Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER.
OMAP-L138 td_emac_rcv_prs345.gif Figure 6-49 EMAC Receive Interface Timing

Table 6-103 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s(1) (see Figure 6-50)

NO. PARAMETER 1.3V, 1.2V, 1.1V 1.0V UNIT
MIN MAX MIN MAX
1 td(MII_TXCLKH-MTXD) Delay time, MII_TXCLK high to transmit selected signals valid 2 25 2 32 ns
Transmit selected signals include: MTXD3-MTXD0, and MII_TXEN.
OMAP-L138 td_emac_xmit_prs345.gif Figure 6-50 EMAC Transmit Interface Timing

Table 6-104 Timing Requirements for EMAC RMII

NO. 1.3V, 1.2V, 1.1V(1) UNIT
MIN TYP MAX
1 tc(REFCLK) Cycle Time, RMII_MHZ_50_CLK 20 ns
2 tw(REFCLKH) Pulse Width, RMII_MHZ_50_CLK High 7 13 ns
3 tw(REFCLKL) Pulse Width, RMII_MHZ_50_CLK Low 7 13 ns
6 tsu(RXD-REFCLK) Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High 4 ns
7 th(REFCLK-RXD) Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High 2 ns
8 tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High 4 ns
9 th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High 2 ns
10 tsu(RXER-REFCLK) Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High 4 ns
11 th(REFCLKR-RXER) Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High 2 ns
RMII is not supported at operating points below 1.1V nominal

Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.

Table 6-105 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII

NO. PARAMETER 1.3V, 1.2V, 1.1V(1) UNIT
MIN TYP MAX
4 td(REFCLK-TXD) Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid 2.5 13 ns
5 td(REFCLK-TXEN) Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid 2.5 13 ns
RMII is not supported at operating points below 1.1V nominal.
OMAP-L138 rmii_tmng1_prs483.gif Figure 6-51 RMII Timing Diagram

Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time.

MDIO Register Description(s)

Table 6-106 MDIO Register Memory Map

BYTE ADDRESS ACRONYM REGISTER NAME
0x01E2 4000 REV Revision Identification Register
0x01E2 4004 CONTROL MDIO Control Register
0x01E2 4008 ALIVE MDIO PHY Alive Status Register
0x01E2 400C LINK MDIO PHY Link Status Register
0x01E2 4010 LINKINTRAW MDIO Link Status Change Interrupt (Unmasked) Register
0x01E2 4014 LINKINTMASKED MDIO Link Status Change Interrupt (Masked) Register
0x01E2 4018 Reserved
0x01E2 4020 USERINTRAW MDIO User Command Complete Interrupt (Unmasked) Register
0x01E2 4024 USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register
0x01E2 4028 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register
0x01E2 402C USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register
0x01E2 4030 - 0x01E2 407C Reserved
0x01E2 4080 USERACCESS0 MDIO User Access Register 0
0x01E2 4084 USERPHYSEL0 MDIO User PHY Select Register 0
0x01E2 4088 USERACCESS1 MDIO User Access Register 1
0x01E2 408C USERPHYSEL1 MDIO User PHY Select Register 1
0x01E2 4090 - 0x01E2 47FF Reserved

Management Data Input/Output (MDIO) Electrical Data/Timing

Table 6-107 Timing Requirements for MDIO Input (see Figure 6-52 and Figure 6-53)

NO. 1.3V, 1.2V, 1.1V 1.0V UNIT
MIN MAX MIN MAX
1 tc(MDCLK) Cycle time, MDCLK 400 400 ns
2 tw(MDCLK) Pulse duration, MDCLK high/low 180 180 ns
3 tt(MDCLK) Transition time, MDCLK 5 5 ns
4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 16 21 ns
5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high 0 0 ns
OMAP-L138 td_mdio_in_prs271.gif Figure 6-52 MDIO Input Timing

Table 6-108 Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-53)

NO. PARAMETER 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid 0 100 ns
OMAP-L138 td_mdio_out_prs271.gif Figure 6-53 MDIO Output Timing

LCD Controller (LCDC)

The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface Display Driver (LIDD) controller. Each controller operates independently from the other and only one of them is active at any given time.

  • The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer. Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn, outputs to the external LCD device.
  • The LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability of control signals (CS, WE, OE, ALE) and output data.

The maximum resolution for the LCD controller is 1024 x 1024 pixels. The maximum frame rate is determined by the image size in combination with the pixel clock rate. For details, see SPRAB93.

Table 6-109 lists the LCD Controller registers.

Table 6-109 LCD Controller Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E1 3000 REVID LCD Revision Identification Register
0x01E1 3004 LCD_CTRL LCD Control Register
0x01E1 3008 LCD_STAT LCD Status Register
0x01E1 300C LIDD_CTRL LCD LIDD Control Register
0x01E1 3010 LIDD_CS0_CONF LCD LIDD CS0 Configuration Register
0x01E1 3014 LIDD_CS0_ADDR LCD LIDD CS0 Address Read/Write Register
0x01E1 3018 LIDD_CS0_DATA LCD LIDD CS0 Data Read/Write Register
0x01E1 301C LIDD_CS1_CONF LCD LIDD CS1 Configuration Register
0x01E1 3020 LIDD_CS1_ADDR LCD LIDD CS1 Address Read/Write Register
0x01E1 3024 LIDD_CS1_DATA LCD LIDD CS1 Data Read/Write Register
0x01E1 3028 RASTER_CTRL LCD Raster Control Register
0x01E1 302C RASTER_TIMING_0 LCD Raster Timing 0 Register
0x01E1 3030 RASTER_TIMING_1 LCD Raster Timing 1 Register
0x01E1 3034 RASTER_TIMING_2 LCD Raster Timing 2 Register
0x01E1 3038 RASTER_SUBPANEL LCD Raster Subpanel Display Register
0x01E1 3040 LCDDMA_CTRL LCD DMA Control Register
0x01E1 3044 LCDDMA_FB0_BASE LCD DMA Frame Buffer 0 Base Address Register
0x01E1 3048 LCDDMA_FB0_CEILING LCD DMA Frame Buffer 0 Ceiling Address Register
0x01E1 304C LCDDMA_FB1_BASE LCD DMA Frame Buffer 1 Base Address Register
0x01E1 3050 LCDDMA_FB1_CEILING LCD DMA Frame Buffer 1 Ceiling Address Register

LCD Interface Display Driver (LIDD Mode)

Table 6-110 Timing Requirements for LCD LIDD Mode

NO. 1.3V, 1.2V, 1.1V 1.0V UNIT
MIN MAX MIN MAX
16 tsu(LCD_D) Setup time, LCD_D[15:0] valid before LCD_MCLK high 7 8 ns
17 th(LCD_D) Hold time, LCD_D[15:0] valid after LCD_MCLK high 0 0 ns

Table 6-111 Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode

NO. PARAMETER 1.3V, 1.2V, 1.1V 1.0V UNIT
MIN MAX MIN MAX
4 td(LCD_D_V) Delay time, LCD_MCLK high to LCD_D[15:0] valid (write) 0 7 0 9 ns
5 td(LCD_D_I) Delay time, LCD_MCLK high to LCD_D[15:0] invalid (write) 0 7 0 9 ns
6 td(LCD_E_A) Delay time, LCD_MCLK high to LCD_AC_ENB_CS low 0 7 0 9 ns
7 td(LCD_E_I) Delay time, LCD_MCLK high to LCD_AC_ENB_CS high 0 7 0 9 ns
8 td(LCD_A_A) Delay time, LCD_MCLK high to LCD_VSYNC low 0 7 0 9 ns
9 td(LCD_A_I) Delay time, LCD_MCLK high to LCD_VSYNC high 0 7 0 9 ns
10 td(LCD_W_A) Delay time, LCD_MCLK high to LCD_HSYNC low 0 7 0 9 ns
11 td(LCD_W_I) Delay time, LCD_MCLK high to LCD_HSYNC high 0 7 0 9 ns
12 td(LCD_STRB_A) Delay time, LCD_MCLK high to LCD_PCLK active 0 7 0 9 ns
13 td(LCD_STRB_I) Delay time, LCD_MCLK high to LCD_PCLK inactive 0 7 0 9 ns
14 td(LCD_D_Z) Delay time, LCD_MCLK high to LCD_D[15:0] in 3-state 0 7 0 9 ns
15 td(Z_LCD_D) Delay time, LCD_MCLK high to LCD_D[15:0] (valid from 3-state) 0 7 0 9 ns
OMAP-L138 lcd_44780_wr_prs377.gif Figure 6-54 Character Display HD44780 Write
OMAP-L138 lcd_44780_rd_prs377.gif Figure 6-55 Character Display HD44780 Read
OMAP-L138 lcd_6800_wr_prs377.gif Figure 6-56 Micro-Interface Graphic Display 6800 Write
OMAP-L138 lcd_6800_rd_prs377.gif Figure 6-57 Micro-Interface Graphic Display 6800 Read
OMAP-L138 lcd_6800_sts_prs377.gif Figure 6-58 Micro-Interface Graphic Display 6800 Status
OMAP-L138 lcd_8080_wr_prs377.gif Figure 6-59 Micro-Interface Graphic Display 8080 Write
OMAP-L138 lcd_8080_rd_prs377.gif Figure 6-60 Micro-Interface Graphic Display 8080 Read
OMAP-L138 lcd_8080_sts_prs377.gif Figure 6-61 Micro-Interface Graphic Display 8080 Status

LCD Raster Mode

Table 6-112 Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode

See Figure 6-62 through Figure 6-66
NO. PARAMETER 1.3V, 1.2V, 1.1V 1.0V UNIT
MIN MAX MIN MAX
1 tc(PIXEL_CLK) Cycle time, pixel clock 26.66 33.33 ns
2 tw(PIXEL_CLK_H) Pulse duration, pixel clock high 10 10 ns
3 tw(PIXEL_CLK_L) Pulse duration, pixel clock low 10 10 ns
4 td(LCD_D_V) Delay time, LCD_PCLK high to LCD_D[15:0] valid (write) 0 7 0 9 ns
5 td(LCD_D_IV) Delay time, LCD_PCLK high to LCD_D[15:0] invalid (write) 0 7 0 9 ns
6 td(LCD_AC_ENB_CS_A) Delay time, LCD_PCLK low to LCD_AC_ENB_CS high 0 7 0 9 ns
7 td(LCD_AC_ENB_CS_I) Delay time, LCD_PCLK low to LCD_AC_ENB_CS low 0 7 0 9 ns
8 td(LCD_VSYNC_A) Delay time, LCD_PCLK low to LCD_VSYNC high 0 7 0 9 ns
9 td(LCD_VSYNC_I) Delay time, LCD_PCLK low to LCD_VSYNC low 0 7 0 9 ns
10 td(LCD_HSYNC_A) Delay time, LCD_PCLK high to LCD_HSYNC high 0 7 0 9 ns
11 td(LCD_HSYNC_I) Delay time, LCD_PCLK high to LCD_HSYNC low 0 7 0 9 ns

Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1) register:

  • Vertical front porch (VFP)
  • Vertical sync pulse width (VSW)
  • Vertical back porch (VBP)
  • Lines per panel (LPP)

Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:

  • Horizontal front porch (HFP)
  • Horizontal sync pulse width (HSW)
  • Horizontal back porch (HBP)
  • Pixels per panel (PPL)

LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2) register:

  • AC bias frequency (ACB)

The display format produced in raster mode is shown in Figure 6-62. An entire frame is delivered one line at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the activation of I/O signal LCD_HSYNC.

OMAP-L138 lcd_rm_frmt_prs301.gif Figure 6-62 LCD Raster-Mode Display Format
OMAP-L138 lcd_rm_actv_prs301.gif Figure 6-63 LCD Raster-Mode Active
OMAP-L138 lcd_rm_pass_prs653.gif Figure 6-64 LCD Raster-Mode Passive
OMAP-L138 lcd_rm_csact_prs483.gif Figure 6-65 LCD Raster-Mode Control Signal Activation
OMAP-L138 lcd_raster_cs_deactivation_prs483.gif Figure 6-66 LCD Raster-Mode Control Signal Deactivation

Host-Port Interface (UHPI)

HPI Device-Specific Information

The device includes a user-configurable 16-bit Host-port interface (HPI16).

The host port interface (UHPI) provides a parallel port interface through which an external host processor can directly access the processor's resources (configuration and program/data memories). The external host device is asynchronous to the CPU clock and functions as a master to the HPI interface. The UHPI enables a host device and the processor to exchange information via internal or external memory. Dedicated address (HPIA) and data (HPID) registers within the UHPI provide the data path between the external host interface and the processor resources. A UHPI control register (HPIC) is available to the host and the CPU for various configuration and interrupt functions.

HPI Peripheral Register Description(s)

Table 6-113 HPI Control Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION COMMENTS
0x01E1 0000 PID Peripheral Identification Register
0x01E1 0004 PWREMU_MGMT HPI power and emulation management register The CPU has read/write access to the PWREMU_MGMT register.
0x01E1 0008 - Reserved
0x01E1 000C GPIO_EN General Purpose IO Enable Register
0x01E1 0010 GPIO_DIR1 General Purpose IO Direction Register 1
0x01E1 0014 GPIO_DAT1 General Purpose IO Data Register 1
0x01E1 0018 GPIO_DIR2 General Purpose IO Direction Register 2
0x01E1 001C GPIO_DAT2 General Purpose IO Data Register 2
0x01E1 0020 GPIO_DIR3 General Purpose IO Direction Register 3
0x01E1 0024 GPIO_DAT3 General Purpose IO Data Register 3
01E1 0028 - Reserved
01E1 002C - Reserved
01E1 0030 HPIC HPI control register The Host and the CPU both have read/write access to the HPIC register.
01E1 0034 HPIA
(HPIAW)(1)
HPI address register (Write) The Host has read/write access to the HPIA registers. The CPU has only read access to the HPIA registers.
01E1 0038 HPIA
(HPIAR)(1)
HPI address register (Read)
01E1 000C - 01E1 07FF - Reserved
There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the Host. The CPU can access HPIAW and HPIAR independently.

HPI Electrical Data/Timing

Table 6-114 Timing Requirements for Host-Port Interface [1.2V, 1.1V](1) (2)

NO. 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
1 tsu(SELV-HSTBL) Setup time, select signals(3) valid before UHPI_HSTROBE low 5 ns
2 th(HSTBL-SELV) Hold time, select signals(3) valid after UHPI_HSTROBE low 2 ns
3 tw(HSTBL) Pulse duration, UHPI_HSTROBE active low 15 ns
4 tw(HSTBH) Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses 2M ns
9 tsu(SELV-HASL) Setup time, selects signals valid before UHPI_HAS low 5 ns
10 th(HASL-SELV) Hold time, select signals valid after UHPI_HAS low 2 ns
11 tsu(HDV-HSTBH) Setup time, host data valid before UHPI_HSTROBE high 5 ns
12 th(HSTBH-HDV) Hold time, host data valid after UHPI_HSTROBE high 2 ns
13 th(HRDYL-HSTBH) Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns
16 tsu(HASL-HSTBL) Setup time, UHPI_HAS low before UHPI_HSTROBE low 5 ns
17 th(HSTBL-HASH) Hold time, UHPI_HAS low after UHPI_HSTROBE low 2 ns
UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
M=SYSCLK2 period in ns.
Select signals include: HCNTL[1:0], HR/W and HHWIL.

Table 6-115 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V](1) (2) (3)

NO. PARAMETER 1.3V, 1.2V 1.1V UNIT
MIN MAX MIN MAX
5 td(HSTBL-HRDYV) Delay time, HSTROBE low to HRDY valid For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can be either first or second half-word)
Case 2: HPIA write following a PREFETCH command (can be either first or second half-word)
Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word)
Case 4: HPIA write and Write FIFO not empty

For HPI Read, HRDY can go high (not ready) for these HPI Read conditions:
Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access)
Case 2: First half-word access of HPID Read without auto-increment

For HPI Read, HRDY stays low (ready) for these HPI Read conditions:
Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access)
Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access)
Case 3: HPIC or HPIA read (applies to either half-word access)
15 17 ns
5a td(HASL-HRDYV) Delay time, HAS low to HRDY valid 15 17 ns
6 ten(HSTBL-HDLZ) Enable time, HD driven from HSTROBE low 1.5 1.5 ns
7 td(HRDYL-HDV) Delay time, HRDY low to HD valid 0 0 ns
8 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 1.5 1.5 ns
14 tdis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high 15 17 ns
15 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid For HPI Read. Applies to conditions where data is already residing in HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO
Case 3: Second half-word of HPID read with or without auto-increment
15 17 ns
18 td(HSTBH-HRDYV) Delay time, HSTROBE high to HRDY valid For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready):
Case 1: HPID write when Write FIFO is full (can happen to either half-word)
Case 2: HPIA write (can happen to either half-word)
Case 3: HPID write without auto-increment (only happens to second half-word)
15 17 ns
M=SYSCLK2 period in ns.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).

Table 6-116 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V](1) (2) (3)

NO. PARAMETER 1.0V UNIT
MIN MAX
5 td(HSTBL-HRDYV) Delay time, HSTROBE low to HRDY valid For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can be either first or second half-word)
Case 2: HPIA write following a PREFETCH command (can be either first or second half-word)
Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word)
Case 4: HPIA write and Write FIFO not empty

For HPI Read, HRDY can go high (not ready) for these HPI Read conditions:
Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access)
Case 2: First half-word access of HPID Read without auto-increment
For HPI Read, HRDY stays low (ready) for these HPI Read conditions:
Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access)
Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access)
Case 3: HPIC or HPIA read (applies to either half-word access)
22 ns
5a td(HASL-HRDYV) Delay time, HAS low to HRDY valid 22 ns
6 ten(HSTBL-HDLZ) Enable time, HD driven from HSTROBE low 1.5 ns
7 td(HRDYL-HDV) Delay time, HRDY low to HD valid 0 ns
8 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 1.5 ns
14 tdis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high 22 ns
15 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid For HPI Read. Applies to conditions where data is already residing in HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO
Case 3: Second half-word of HPID read with or without auto-increment
22 ns
18 td(HSTBH-HRDYV) Delay time, HSTROBE high to HRDY valid For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready):
Case 1: HPID write when Write FIFO is full (can happen to either half-word)
Case 2: HPIA write (can happen to either half-word)
Case 3: HPID write without auto-increment (only happens to second half-word)
22 ns
M=SYSCLK2 period in ns.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
OMAP-L138 td2_h16_rd_prs563.gif Figure 6-67 UHPI Read Timing (HAS Not Used, Tied High)
OMAP-L138 td1_hpi_rd_prs563.gif
For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-68 UHPI Read Timing (HAS Used)
OMAP-L138 td4_h16_wrt_prs563.gif Figure 6-69 UHPI Write Timing (HAS Not Used, Tied High)
OMAP-L138 td_hpi_wr_prs563.gif
For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-70 UHPI Write Timing (HAS Used)

Universal Parallel Port (uPP)

The Universal Parallel Port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels operate in opposite directions.

The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O channel. In this mode, only one I/O channel may be used.

The features of the uPP include:

  • Programmable data width per channel (from 8 to 16 bits inclusive)
  • Programmable data justification
    • Right-justify with zero extend
    • Right-justify with sign extend
    • Left-justify with zero fill
  • Supports multiplexing of interleaved data during SDR transmit
  • Optional frame START signal with programmable polarity
  • Optional data ENABLE signal with programmable polarity
  • Optional synchronization WAIT signal with programmable polarity
  • Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface
    • Supports multiplexing of interleaved data during SDR transmit
    • Supports demultiplexing and multiplexing of interleaved data during DDR transfers

For detailed information on the uPP, see the <peripheral guide reference TBD>.

uPP Register Descriptions

Table 6-117 Universal Parallel Port (uPP) Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E1 6000 UPPID uPP Peripheral Identification Register
0x01E1 6004 UPPCR uPP Peripheral Control Register
0x01E1 6008 UPDLB uPP Digital Loopback Register
0x01E1 6010 UPCTL uPP Channel Control Register
0x01E1 6014 UPICR uPP Interface Configuration Register
0x01E1 6018 UPIVR uPP Interface Idle Value Register
0x01E1 601C UPTCR uPP Threshold Configuration Register
0x01E1 6020 UPISR uPP Interrupt Raw Status Register
0x01E1 6024 UPIER uPP Interrupt Enabled Status Register
0x01E1 6028 UPIES uPP Interrupt Enable Set Register
0x01E1 602C UPIEC uPP Interrupt Enable Clear Register
0x01E1 6030 UPEOI uPP End-of-Interrupt Register
0x01E1 6040 UPID0 uPP DMA Channel I Descriptor 0 Register
0x01E1 6044 UPID1 uPP DMA Channel I Descriptor 1 Register
0x01E1 6048 UPID2 uPP DMA Channel I Descriptor 2 Register
0x01E1 6050 UPIS0 uPP DMA Channel I Status 0 Register
0x01E1 6054 UPIS1 uPP DMA Channel I Status 1 Register
0x01E1 6058 UPIS2 uPP DMA Channel I Status 2 Register
0x01E1 6060 UPQD0 uPP DMA Channel Q Descriptor 0 Register
0x01E1 6064 UPQD1 uPP DMA Channel Q Descriptor 1 Register
0x01E1 6068 UPQD2 uPP DMA Channel Q Descriptor 2 Register
0x01E1 6070 UPQS0 uPP DMA Channel Q Status 0 Register
0x01E1 6074 UPQS1 uPP DMA Channel Q Status 1 Register
0x01E1 6078 UPQS2 uPP DMA Channel Q Status 2 Register

uPP Electrical Data/Timing

Table 6-118 Timing Requirements for uPP (see Figure 6-71, Figure 6-72, Figure 6-73, Figure 6-74)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tc(INCLK) Cycle time, CHn_CLK SDR mode 13.33 20 26.66 ns
DDR mode 26.66 40 53.33
2 tw(INCLKH) Pulse width, CHn_CLK high SDR mode 5 8 10 ns
DDR mode 10 16 20
3 tw(INCLKL) Pulse width, CHn_CLK low SDR mode 5 8 10 ns
DDR mode 10 16 20
4 tsu(STV-INCLKH) Setup time, CHn_START valid before CHn_CLK high 4 5.5 6.5 ns
5 th(INCLKH-STV) Hold time, CHn_START valid after CHn_CLK high 0.8 0.8 0.8 ns
6 tsu(ENV-INCLKH) Setup time, CHn_ENABLE valid before CHn_CLK high 4 5.5 6.5 ns
7 th(INCLKH-ENV) Hold time, CHn_ENABLE valid after CHn_CLK high 0.8 0.8 0.8 ns
8 tsu(DV-INCLKH) Setup time,
CHn_DATA/XDATA valid before CHn_CLK high
4 5.5 6.5 ns
9 th(INCLKH-DV) Hold time, CHn_DATA/XDATA valid after CHn_CLK high 0.8 0.8 0.8 ns
10 tsu(DV-INCLKL) Setup time, CHn_DATA/XDATA valid before CHn_CLK low 4 5.5 6.5 ns
11 th(INCLKL-DV) Hold time, CHn_DATA/XDATA valid after CHn_CLK low 0.8 0.8 0.8 ns
19 tsu(WTV-INCLKL) Setup time, CHn_WAIT valid before CHn_CLK high 10 12 14 ns
20 th(INCLKL-WTV) Hold time, CHn_WAIT valid after CHn_CLK high 0.8 0.8 0.8 ns
21 tc(2xTXCLK) Cycle time, 2xTXCLK input clock(1) 6.66 10 13.33 ns
2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.

Table 6-119 Switching Characteristics Over Recommended Operating Conditions for uPP

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
12 tc(OUTCLK) Cycle time, CHn_CLK SDR mode 13.33 20 26.66 ns
DDR mode 26.66 40 53.33
13 tw(OUTCLKH) Pulse width, CHn_CLK high SDR mode 5 8 10 ns
DDR mode 10 16 20
14 tw(OUTCLKL) Pulse width, CHn_CLK low SDR mode 5 8 10 ns
DDR mode 10 16 20
15 td(OUTCLKH-STV) Delay time, CHn_START valid after CHn_CLK high 2 11 2 15 2 21 ns
16 td(OUTCLKH-ENV) Delay time, CHn_ENABLE valid after CHn_CLK high 2 11 2 15 2 21 ns
17 td(OUTCLKH-DV) Delay time, CHn_DATA/XDATA valid after CHn_CLK high 2 11 2 15 2 21 ns
18 td(OUTCLKL-DV) Delay time, CHn_DATA/XDATA valid after CHn_CLK low 2 11 2 15 2 21 ns
OMAP-L138 upp_freon_timing1_prs586.gif Figure 6-71 uPP Single Data Rate (SDR) Receive Timing
OMAP-L138 upp_freon_timing2_prs586.gif Figure 6-72 uPP Double Data Rate (DDR) Receive Timing
OMAP-L138 upp_freon_timing3_prs586.gif Figure 6-73 uPP Single Data Rate (SDR) Transmit Timing
OMAP-L138 upp_freon_timing4_prs586.gif Figure 6-74 uPP Double Data Rate (DDR) Transmit Timing

Video Port Interface (VPIF)

The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include:

  • Up to 2 Video Capture Channels (Channel 0 and Channel 1)
    • Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)
    • Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)
    • Single Raw Video (8-/10-/12-bit)
  • Up to 2 Video Display Channels (Channel 2 and Channel 3)
    • Two 8-bit SD Video Display with embedded timing codes (BT.656)
    • Single 16-bit HD Video Display with embedded timing codes (BT.1120)

The VPIF capture channel input data format is selectable based on the settings of the specific Channel Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings of the Channel 0 Control Register.

VPIF Register Descriptions

Table 6-120 shows the VPIF registers.

Table 6-120 Video Port Interface (VPIF) Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E1 7000 PID Peripheral identification register
0x01E1 7004 CH0_CTRL Channel 0 control register
0x01E1 7008 CH1_CTRL Channel 1 control register
0x01E1 700C CH2_CTRL Channel 2 control register
0x01E1 7010 CH3_CTRL Channel 3 control register
0x01E1 7014 - 0x01E1 701F - Reserved
0x01E1 7020 INTEN Interrupt enable
0x01E1 7024 INTENSET Interrupt enable set
0x01E1 7028 INTENCLR Interrupt enable clear
0x01E1 702C INTSTAT Interrupt status
0x01E1 7030 INTSTATCLR Interrupt status clear
0x01E1 7034 EMU_CTRL Emulation control
0x01E1 7038 DMA_SIZE DMA size control
0x01E1 703C - 0x01E1 703F - Reserved
CAPTURE CHANNEL 0 REGISTERS
0x01E1 7040 CH0_TY_STRTADR Channel 0 Top Field luma buffer start address
0x01E1 7044 CH0_BY_STRTADR Channel 0 Bottom Field luma buffer start address
0x01E1 7048 CH0_TC_STRTADR Channel 0 Top Field chroma buffer start address
0x01E1 704C CH0_BC_STRTADR Channel 0 Bottom Field chroma buffer start address
0x01E1 7050 CH0_THA_STRTADR Channel 0 Top Field horizontal ancillary data buffer start address
0x01E1 7054 CH0_BHA_STRTADR Channel 0 Bottom Field horizontal ancillary data buffer start address
0x01E1 7058 CH0_TVA_STRTADR Channel 0 Top Field vertical ancillary data buffer start address
0x01E1 705C CH0_BVA_STRTADR Channel 0 Bottom Field vertical ancillary data buffer start address
0x01E1 7060 CH0_SUBPIC_CFG Channel 0 sub-picture configuration
0x01E1 7064 CH0_IMG_ADD_OFST Channel 0 image data address offset
0x01E1 7068 CH0_HA_ADD_OFST Channel 0 horizontal ancillary data address offset
0x01E1 706C CH0_HSIZE_CFG Channel 0 horizontal data size configuration
0x01E1 7070 CH0_VSIZE_CFG0 Channel 0 vertical data size configuration (0)
0x01E1 7074 CH0_VSIZE_CFG1 Channel 0 vertical data size configuration (1)
0x01E1 7078 CH0_VSIZE_CFG2 Channel 0 vertical data size configuration (2)
0x01E1 707C CH0_VSIZE Channel 0 vertical image size
CAPTURE CHANNEL 1 REGISTERS
0x01E1 7080 CH1_TY_STRTADR Channel 1 Top Field luma buffer start address
0x01E1 7084 CH1_BY_STRTADR Channel 1 Bottom Field luma buffer start address
0x01E1 7088 CH1_TC_STRTADR Channel 1 Top Field chroma buffer start address
0x01E1 708C CH1_BC_STRTADR Channel 1 Bottom Field chroma buffer start address
0x01E1 7090 CH1_THA_STRTADR Channel 1 Top Field horizontal ancillary data buffer start address
0x01E1 7094 CH1_BHA_STRTADR Channel 1 Bottom Field horizontal ancillary data buffer start address
0x01E1 7098 CH1_TVA_STRTADR Channel 1 Top Field vertical ancillary data buffer start address
0x01E1 709C CH1_BVA_STRTADR Channel 1 Bottom Field vertical ancillary data buffer start address
0x01E1 70A0 CH1_SUBPIC_CFG Channel 1 sub-picture configuration
0x01E1 70A4 CH1_IMG_ADD_OFST Channel 1 image data address offset
0x01E1 70A8 CH1_HA_ADD_OFST Channel 1 horizontal ancillary data address offset
0x01E1 70AC CH1_HSIZE_CFG Channel 1 horizontal data size configuration
0x01E1 70B0 CH1_VSIZE_CFG0 Channel 1 vertical data size configuration (0)
0x01E1 70B4 CH1_VSIZE_CFG1 Channel 1 vertical data size configuration (1)
0x01E1 70B8 CH1_VSIZE_CFG2 Channel 1 vertical data size configuration (2)
0x01E1 70BC CH1_VSIZE Channel 1 vertical image size
DISPLAY CHANNEL 2 REGISTERS
0x01E1 70C0 CH2_TY_STRTADR Channel 2 Top Field luma buffer start address
0x01E1 70C4 CH2_BY_STRTADR Channel 2 Bottom Field luma buffer start address
0x01E1 70C8 CH2_TC_STRTADR Channel 2 Top Field chroma buffer start address
0x01E1 70CC CH2_BC_STRTADR Channel 2 Bottom Field chroma buffer start address
0x01E1 70D0 CH2_THA_STRTADR Channel 2 Top Field horizontal ancillary data buffer start address
0x01E1 70D4 CH2_BHA_STRTADR Channel 2 Bottom Field horizontal ancillary data buffer start address
0x01E1 70D8 CH2_TVA_STRTADR Channel 2 Top Field vertical ancillary data buffer start address
0x01E1 70DC CH2_BVA_STRTADR Channel 2 Bottom Field vertical ancillary data buffer start address
0x01E1 70E0 CH2_SUBPIC_CFG Channel 2 sub-picture configuration
0x01E1 70E4 CH2_IMG_ADD_OFST Channel 2 image data address offset
0x01E1 70E8 CH2_HA_ADD_OFST Channel 2 horizontal ancillary data address offset
0x01E1 70EC CH2_HSIZE_CFG Channel 2 horizontal data size configuration
0x01E1 70F0 CH2_VSIZE_CFG0 Channel 2 vertical data size configuration (0)
0x01E1 70F4 CH2_VSIZE_CFG1 Channel 2 vertical data size configuration (1)
0x01E1 70F8 CH2_VSIZE_CFG2 Channel 2 vertical data size configuration (2)
0x01E1 70FC CH2_VSIZE Channel 2 vertical image size
0x01E1 7100 CH2_THA_STRTPOS Channel 2 Top Field horizontal ancillary data insertion start position
0x01E1 7104 CH2_THA_SIZE Channel 2 Top Field horizontal ancillary data size
0x01E1 7108 CH2_BHA_STRTPOS Channel 2 Bottom Field horizontal ancillary data insertion start position
0x01E1 710C CH2_BHA_SIZE Channel 2 Bottom Field horizontal ancillary data size
0x01E1 7110 CH2_TVA_STRTPOS Channel 2 Top Field vertical ancillary data insertion start position
0x01E1 7114 CH2_TVA_SIZE Channel 2 Top Field vertical ancillary data size
0x01E1 7118 CH2_BVA_STRTPOS Channel 2 Bottom Field vertical ancillary data insertion start position
0x01E1 711C CH2_BVA_SIZE Channel 2 Bottom Field vertical ancillary data size
0x01E1 7120 - 0x01E1 713F - Reserved
DISPLAY CHANNEL 3 REGISTERS
0x01E1 7140 CH3_TY_STRTADR Channel 3 Field 0 luma buffer start address
0x01E1 7144 CH3_BY_STRTADR Channel 3 Field 1 luma buffer start address
0x01E1 7148 CH3_TC_STRTADR Channel 3 Field 0 chroma buffer start address
0x01E1 714C CH3_BC_STRTADR Channel 3 Field 1 chroma buffer start address
0x01E1 7150 CH3_THA_STRTADR Channel 3 Field 0 horizontal ancillary data buffer start address
0x01E1 7154 CH3_BHA_STRTADR Channel 3 Field 1 horizontal ancillary data buffer start address
0x01E1 7158 CH3_TVA_STRTADR Channel 3 Field 0 vertical ancillary data buffer start address
0x01E1 715C CH3_BVA_STRTADR Channel 3 Field 1 vertical ancillary data buffer start address
0x01E1 7160 CH3_SUBPIC_CFG Channel 3 sub-picture configuration
0x01E1 7164 CH3_IMG_ADD_OFST Channel 3 image data address offset
0x01E1 7168 CH3_HA_ADD_OFST Channel 3 horizontal ancillary data address offset
0x01E1 716C CH3_HSIZE_CFG Channel 3 horizontal data size configuration
0x01E1 7170 CH3_VSIZE_CFG0 Channel 3 vertical data size configuration (0)
0x01E1 7174 CH3_VSIZE_CFG1 Channel 3 vertical data size configuration (1)
0x01E1 7178 CH3_VSIZE_CFG2 Channel 3 vertical data size configuration (2)
0x01E1 717C CH3_VSIZE Channel 3 vertical image size
0x01E1 7180 CH3_THA_STRTPOS Channel 3 Top Field horizontal ancillary data insertion start position
0x01E1 7184 CH3_THA_SIZE Channel 3 Top Field horizontal ancillary data size
0x01E1 7188 CH3_BHA_STRTPOS Channel 3 Bottom Field horizontal ancillary data insertion start position
0x01E1 718C CH3_BHA_SIZE Channel 3 Bottom Field horizontal ancillary data size
0x01E1 7190 CH3_TVA_STRTPOS Channel 3 Top Field vertical ancillary data insertion start position
0x01E1 7194 CH3_TVA_SIZE Channel 3 Top Field vertical ancillary data size
0x01E1 7198 CH3_BVA_STRTPOS Channel 3 Bottom Field vertical ancillary data insertion start position
0x01E1 719C CH3_BVA_SIZE Channel 3 Bottom Field vertical ancillary data size
0x01E1 71A0 - 0x01E1 71FF - Reserved

VPIF Electrical Data/Timing

Table 6-121 Timing Requirements for VPIF VP_CLKINx Inputs(1) (see Figure 6-75)

NO. 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tc(VKI) Cycle time, VP_CLKIN0 13.3 20 37 ns
Cycle time, VP_CLKIN1/2/3 13.3 20 37 ns
2 tw(VKIH) Pulse duration, VP_CLKINx high 0.4C 0.4C 0.4C ns
3 tw(VKIL) Pulse duration, VP_CLKINx low 0.4C 0.4C 0.4C ns
4 tt(VKI) Transition time, VP_CLKINx 5 5 5 ns
C = VP_CLKINx period in ns.
OMAP-L138 td_vpx_prs403.gif Figure 6-75 Video Port Capture VP_CLKINx Timing

Table 6-122 Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs
(see Figure 6-76)

NO. 1.3V 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 tsu(VDINV-VKIH) Setup time, VP_DINx valid before VP_OSCIN0/1 high 4 4 6 7 ns
2 th(VKIH-VDINV) Hold time, VP_DINx valid after VP_CLKIN0/1 high 0.5 0 0 0 ns
OMAP-L138 td_vp_in_prs403.gif Figure 6-76 VPIF Channels 0/1 Video Capture Data and Control Input Timing

Table 6-123 Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3(1)
(see Figure 6-77)

NO. PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
1 tc(VKO) Cycle time, VP_CLKOUT2/3 13.3 20 37 ns
2 tw(VKOH) Pulse duration, VP_CLKOUT2/3 high 0.4C 0.4C 0.4C ns
3 tw(VKOL) Pulse duration, VP_CLKOUT2/3 low 0.4C 0.4C 0.4C ns
4 tt(VKO) Transition time, VP_CLKOUT2/3 5 5 5 ns
11 td(VKOH-VPDOUTV) Delay time,
VP_CLKOUT2/3 high to VP_DOUTx valid
8.5 12 17 ns
12 td(VCLKOH-VPDOUTIV) Delay time,
VP_CLKOUT2/3 high to VP_DOUTx invalid
1.5 1.5 1.5 ns
C = VP_CLKO2/3 period in ns.
OMAP-L138 td_vp_out_prs403.gif Figure 6-77 VPIF Channels 2/3 Video Display Data Output Timing With Respect to VP_CLKOUT2/3

Enhanced Capture (eCAP) Peripheral

The device contains up to three enhanced capture (eCAP) modules. Figure 6-78 shows a functional block diagram of a module.

Uses for ECAP include:

  • Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
  • Elapsed time measurements between position sensor triggers
  • Period and duty cycle measurements of pulse train signals
  • Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors

The ECAP module described in this specification includes the following features:

  • 32 bit time base
  • 4 event time-stamp registers (each 32 bits)
  • Edge polarity selection for up to 4 sequenced time-stamp capture events
  • Interrupt on either of the 4 events
  • Single shot capture of up to 4 event time-stamps
  • Continuous mode capture of time-stamps in a 4 deep circular buffer
  • Absolute time-stamp capture
  • Difference mode time-stamp capture
  • All the above resources are dedicated to a single input pin

The eCAP modules are clocked at the ASYNC3 clock domain rate.

OMAP-L138 fbd_ecap_prs230.gif Figure 6-78 eCAP Functional Block Diagram

Table 6-124 is the list of the ECAP registers.

Table 6-124 ECAPx Configuration Registers

ECAP0
BYTE ADDRESS
ECAP1
BYTE ADDRESS
ECAP2
BYTE ADDRESS
ACRONYM DESCRIPTION
0x01F0 6000 0x01F0 7000 0x01F0 8000 TSCTR Time-Stamp Counter
0x01F0 6004 0x01F0 7004 0x01F0 8004 CTRPHS Counter Phase Offset Value Register
0x01F0 6008 0x01F0 7008 0x01F0 8008 CAP1 Capture 1 Register
0x01F0 600C 0x01F0 700C 0x01F0 800C CAP2 Capture 2 Register
0x01F0 6010 0x01F0 7010 0x01F0 8010 CAP3 Capture 3 Register
0x01F0 6014 0x01F0 7014 0x01F0 8014 CAP4 Capture 4 Register
0x01F0 6028 0x01F0 7028 0x01F0 8028 ECCTL1 Capture Control Register 1
0x01F0 602A 0x01F0 702A 0x01F0 802A ECCTL2 Capture Control Register 2
0x01F0 602C 0x01F0 702C 0x01F0 802C ECEINT Capture Interrupt Enable Register
0x01F0 602E 0x01F0 702E 0x01F0 802E ECFLG Capture Interrupt Flag Register
0x01F0 6030 0x01F0 7030 0x01F0 8030 ECCLR Capture Interrupt Clear Register
0x01F0 6032 0x01F0 7032 0x01F0 8032 ECFRC Capture Interrupt Force Register
0x01F0 605C 0x01F0 705C 0x01F0 805C REVID Revision ID

Table 6-125 shows the eCAP timing requirement and Table 6-126 shows the eCAP switching characteristics.

Table 6-125 Timing Requirements for Enhanced Capture (eCAP)

TEST CONDITIONS 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles

Table 6-126 Switching Characteristics Over Recommended Operating Conditions for eCAP

PARAMETER 1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
tw(APWM) Pulse duration, APWMx output high/low 20 20 20 ns

Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)

The device contains two enhanced PWM Modules (eHRPWM). Figure 6-79 shows a block diagram of multiple eHRPWM modules. Figure 6-79 shows the signal interconnections with the eHRPWM.

OMAP-L138 fbd_pwm_prs586.gif Figure 6-79 Multiple PWM Modules in a OMAP-L138 System
OMAP-L138 fbd_hires_prs230.gif Figure 6-80 eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections

Table 6-127 eHRPWM Module Control and Status Registers Grouped by Submodule

eHRPWM0
BYTE ADDRESS
eHRPWM1
BYTE ADDRESS
ACRONYM SHADOW REGISTER DESCRIPTION
Time-Base Submodule Registers
0x01F0 0000 0x01F0 2000 TBCTL No Time-Base Control Register
0x01F0 0002 0x01F0 2002 TBSTS No Time-Base Status Register
0x01F0 0004 0x01F0 2004 TBPHSHR No Extension for HRPWM Phase Register(1)
0x01F0 0006 0x01F0 2006 TBPHS No Time-Base Phase Register
0x01F0 0008 0x01F0 2008 TBCNT No Time-Base Counter Register
0x01F0 000A 0x01F0 200A TBPRD Yes Time-Base Period Register
Counter-Compare Submodule Registers
0x01F0 000E 0x01F0 200E CMPCTL No Counter-Compare Control Register
0x01F0 0010 0x01F0 2010 CMPAHR No Extension for HRPWM Counter-Compare A Register(1)
0x01F0 0012 0x01F0 2012 CMPA Yes Counter-Compare A Register
0x01F0 0014 0x01F0 2014 CMPB Yes Counter-Compare B Register
Action-Qualifier Submodule Registers
0x01F0 0016 0x01F0 2016 AQCTLA No Action-Qualifier Control Register for Output A (eHRPWMxA)
0x01F0 0018 0x01F0 2018 AQCTLB No Action-Qualifier Control Register for Output B (eHRPWMxB)
0x01F0 001A 0x01F0 201A AQSFRC No Action-Qualifier Software Force Register
0x01F0 001C 0x01F0 201C AQCSFRC Yes Action-Qualifier Continuous S/W Force Register Set
Dead-Band Generator Submodule Registers
0x01F0 001E 0x01F0 201E DBCTL No Dead-Band Generator Control Register
0x01F0 0020 0x01F0 2020 DBRED No Dead-Band Generator Rising Edge Delay Count Register
0x01F0 0022 0x01F0 2022 DBFED No Dead-Band Generator Falling Edge Delay Count Register
PWM-Chopper Submodule Registers
0x01F0 003C 0x01F0 203C PCCTL No PWM-Chopper Control Register
Trip-Zone Submodule Registers
0x01F0 0024 0x01F0 2024 TZSEL No Trip-Zone Select Register
0x01F0 0028 0x01F0 2028 TZCTL No Trip-Zone Control Register
0x01F0 002A 0x01F0 202A TZEINT No Trip-Zone Enable Interrupt Register
0x01F0 002C 0x01F0 202C TZFLG No Trip-Zone Flag Register
0x01F0 002E 0x01F0 202E TZCLR No Trip-Zone Clear Register
0x01F0 0030 0x01F0 2030 TZFRC No Trip-Zone Force Register
Event-Trigger Submodule Registers
0x01F0 0032 0x01F0 2032 ETSEL No Event-Trigger Selection Register
0x01F0 0034 0x01F0 2034 ETPS No Event-Trigger Pre-Scale Register
0x01F0 0036 0x01F0 2036 ETFLG No Event-Trigger Flag Register
0x01F0 0038 0x01F0 2038 ETCLR No Event-Trigger Clear Register
0x01F0 003A 0x01F0 203A ETFRC No Event-Trigger Force Register
High-Resolution PWM (HRPWM) Submodule Registers
0x01F0 1040 0x01F0 3040 HRCNFG No HRPWM Configuration Register (1)
These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these locations are reserved.

Enhanced Pulse Width Modulator (eHRPWM) Timing

PWM refers to PWM outputs on eHRPWM1-6. Table 6-128 shows the PWM timing requirements and Table 6-129, switching characteristics.

Table 6-128 Timing Requirements for eHRPWM

TEST CONDITIONS 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
tw(SYNCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles

Table 6-129 Switching Characteristics Over Recommended Operating Conditions for eHRPWM

PARAMETER TEST
CONDITIONS
1.3V, 1.2V 1.1V 1.0V UNIT
MIN MAX MIN MAX MIN MAX
tw(PWM) Pulse duration, PWMx output high/low 20 20 26.6 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) 8tc(SCO) 8tc(SCO) cycles
td(PWM)TZA Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load; no additional programmable delay 25 25 25 ns
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z no additional programmable delay 20 20 20 ns

Trip-Zone Input Timing

OMAP-L138 td_pwmhz_prs230.gif
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 6-81 PWM Hi-Z Characteristics

Table 6-130 Trip-Zone input Timing Requirements

TEST CONDITIONS 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
tw(TZ) Pulse duration, TZx input low Asynchronous 1tc(SCO) cycles
Synchronous 2tc(SCO) cycles

Timers

The timers support the following features:

  • Configurable as single 64-bit timer or two 32-bit timers
  • Period timeouts generate interrupts, DMA events or external pin events
  • 8 32-bit compare registers
  • Compare matches generate interrupt events
  • Capture capability
  • 64-bit Watchdog capability (Timer64P1 only)
Table 6-131 lists the timer registers.

Table 6-131 Timer Registers

TIMER64P 0
BYTE
ADDRESS
TIMER64P 1
BYTE
ADDRESS
TIMER64P 2
BYTE
ADDRESS
TIMER64P 3
BYTE
ADDRESS
ACRONYM REGISTER DESCRIPTION
0x01C2 0000 0x01C2 1000 0x01F0 C000 0x01F0 D000 REV Revision Register
0x01C2 0004 0x01C2 1004 0x01F0 C004 0x01F0 D004 EMUMGT Emulation Management Register
0x01C2 0008 0x01C2 1008 0x01F0 C008 0x01F0 D008 GPINTGPEN GPIO Interrupt and GPIO Enable Register
0x01C2 000C 0x01C2 100C 0x01F0 C00C 0x01F0 D00C GPDATGPDIR GPIO Data and GPIO Direction Register
0x01C2 0010 0x01C2 1010 0x01F0 C010 0x01F0 D010 TIM12 Timer Counter Register 12
0x01C2 0014 0x01C2 1014 0x01F0 C014 0x01F0 D014 TIM34 Timer Counter Register 34
0x01C2 0018 0x01C2 1018 0x01F0 C018 0x01F0 D018 PRD12 Timer Period Register 12
0x01C2 001C 0x01C2 101C 0x01F0 C01C 0x01F0 D01C PRD34 Timer Period Register 34
0x01C2 0020 0x01C2 1020 0x01F0 C020 0x01F0 D020 TCR Timer Control Register
0x01C2 0024 0x01C2 1024 0x01F0 C024 0x01F0 D024 TGCR Timer Global Control Register
0x01C2 0028 0x01C2 1028 0x01F0 C028 0x01F0 D028 WDTCR Watchdog Timer Control Register
0x01C2 0034 0x01C2 1034 0x01F0 C034 0x01F0 D034 REL12 Timer Reload Register 12
0x01C2 0038 0x01C2 1038 0x01F0 C038 0x01F0 D038 REL34 Timer Reload Register 34
0x01C2 003C 0x01C2 103C 0x01F0 C03C 0x01F0 D03C CAP12 Timer Capture Register 12
0x01C2 0040 0x01C2 1040 0x01F0 C040 0x01F0 D040 CAP34 Timer Capture Register 34
0x01C2 0044 0x01C2 1044 0x01F0 C044 0x01F0 D044 INTCTLSTAT Timer Interrupt Control and Status Register
0x01C2 0060 0x01C2 1060 0x01F0 C060 0x01F0 D060 CMP0 Compare Register 0
0x01C2 0064 0x01C2 1064 0x01F0 C064 0x01F0 D064 CMP1 Compare Register 1
0x01C2 0068 0x01C2 1068 0x01F0 C068 0x01F0 D068 CMP2 Compare Register 2
0x01C2 006C 0x01C2 106C 0x01F0 C06C 0x01F0 D06C CMP3 Compare Register 3
0x01C2 0070 0x01C2 1070 0x01F0 C070 0x01F0 D070 CMP4 Compare Register 4
0x01C2 0074 0x01C2 1074 0x01F0 C074 0x01F0 D074 CMP5 Compare Register 5
0x01C2 0078 0x01C2 1078 0x01F0 C078 0x01F0 D078 CMP6 Compare Register 6
0x01C2 007C 0x01C2 107C 0x01F0 C07C 0x01F0 D07C CMP7 Compare Register 7

Timer Electrical Data/Timing

Table 6-132 Timing Requirements for Timer Input(1) (2) (see Figure 6-82)

NO. 1.3V, 1.2V, 1.1V, 1.0V UNIT
MIN MAX
1 tc(TM64Px_IN12) Cycle time, TM64Px_IN12 4P ns
2 tw(TINPH) Pulse duration, TM64Px_IN12 high 0.45C 0.55C ns
3 tw(TINPL) Pulse duration, TM64Px_IN12 low 0.45C 0.55C ns
4 tt(TM64Px_IN12) Transition time, TM64Px_IN12 0.25P or 10 (3) ns
P = OSCIN cycle time in ns.
C = TM64P0_IN12 cycle time in ns.
Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.
OMAP-L138 td_timer_prs271.gif Figure 6-82 Timer Timing

Table