Product details

Arm CPU 1 Arm9 Arm MHz (Max.) 456 Co-processor(s) C674x DSP CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection, Secure boot Rating Catalog Operating temperature range (C) -40 to 105, -40 to 90, 0 to 90
Arm CPU 1 Arm9 Arm MHz (Max.) 456 Co-processor(s) C674x DSP CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection, Secure boot Rating Catalog Operating temperature range (C) -40 to 105, -40 to 90, 0 to 90
NFBGA (ZCE) 361 NFBGA (ZWT) 361 256 mm² 16 x 16
  • Dual-Core SoC
    • 375- and 456-MHz ARM926EJ-S RISC MPU
    • 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
  • ARM926EJ-S Core
    • 32- and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single-Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2746 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture With Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • Software Support
    • TI DSPBIOS
    • Chip Support Library and DSP Library
  • 128KB of RAM Shared Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM With 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller With one of the Following:
      • 16-Bit DDR2 SDRAM With 256-MB Address Space
      • 16-Bit mDDR SDRAM With 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
  • Serial ATA (SATA) Controller:
    • Supports SATA I (1.5 Gbps) and SATA II
      (3.0 Gbps)
    • Supports All SATA Power-Management Features
    • Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball Pb-Free PBGA [ZWT Suffix],
      0.80-mm Ball Pitch
  • Commercial, Extended, or Industrial Temperature

All trademarks are the property of their respective owners.

  • Dual-Core SoC
    • 375- and 456-MHz ARM926EJ-S RISC MPU
    • 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
  • ARM926EJ-S Core
    • 32- and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single-Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2746 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture With Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • Software Support
    • TI DSPBIOS
    • Chip Support Library and DSP Library
  • 128KB of RAM Shared Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM With 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller With one of the Following:
      • 16-Bit DDR2 SDRAM With 256-MB Address Space
      • 16-Bit mDDR SDRAM With 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
  • Serial ATA (SATA) Controller:
    • Supports SATA I (1.5 Gbps) and SATA II
      (3.0 Gbps)
    • Supports All SATA Power-Management Features
    • Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball Pb-Free PBGA [ZWT Suffix],
      0.80-mm Ball Pitch
  • Commercial, Extended, or Industrial Temperature

All trademarks are the property of their respective owners.

The OMAP-L138 C6000 DSP+ARM processor is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The dual-core architecture of the device provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM9 core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM9 core has separate 16-KB instruction and 16-KB data caches. Both caches are 4-way associative with virtual index virtual tag (VIVT). The ARM9 core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by the ARM9 and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust,” the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects the users’ IP and lets them securely set up the system and begin device operation with known, trusted code.

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but also offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, see the .

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The Serial ATA (SATA) controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) provides a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM9 and DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The OMAP-L138 C6000 DSP+ARM processor is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The dual-core architecture of the device provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM9 core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM9 core has separate 16-KB instruction and 16-KB data caches. Both caches are 4-way associative with virtual index virtual tag (VIVT). The ARM9 core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by the ARM9 and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust,” the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects the users’ IP and lets them securely set up the system and begin device operation with known, trusted code.

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but also offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, see the .

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The Serial ATA (SATA) controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) provides a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM9 and DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

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Technical documentation

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Type Title Date
* Data sheet OMAP-L138 C6000 DSP+ARM Processor datasheet (Rev. J) 31 Jan 2017
* Errata OMAP-L138 C6000 DSP+ARM Processor (Revs 2.3, 2.1, 2.0, 1.1, & 1.0) Errata (Rev. M) 21 Mar 2014
* User guide OMAP-L138 C6000 DSP+ARM Processor Technical Reference Manual (Rev. C) 09 Sep 2016
Application note OMAPL138/C6748 ROM Bootloader Resources and FAQ (Rev. A) 21 Jan 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Y) 04 Feb 2020
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. V) 04 Feb 2020
Application note Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x 20 Dec 2019
User guide L138/C6748 development kit (LCDK) (Rev. A) 18 Sep 2019
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling 11 Jun 2019
Application note TDA2x/TDA2E Performance (Rev. A) 10 Jun 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 03 Jun 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 03 Jun 2019
Application note Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx 25 Apr 2019
Application note OMAP-L132/L138 Power Consumption Summary 01 Apr 2019
Application note General Hardware Design/BGA PCB Design/BGA 22 Feb 2019
Application note OMAP-L13x / C674x / AM1x schematic review guidelines 14 Feb 2019
Application note Using the OMAP-L132/L138 Bootloader Application Report (Rev. F) 22 Jan 2019
Application note McASP Design Guide - Tips, Tricks, and Practical Examples 10 Jan 2019
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 19 Nov 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 19 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
White paper Designing professional audio mixers for every scenario 28 Jun 2018
User guide PRU Assembly Instruction User Guide 16 Feb 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 16 Jan 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 16 Jan 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 30 Sep 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 30 Sep 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 21 Jun 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 21 Jun 2017
Application note Processor SDK RTOS Audio Benchmark Starter Kit 12 Apr 2017
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 30 Apr 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 30 Apr 2016
Technical article Enabling Wi-Fi® and Bluetooth® connectivity on RTOS 13 Apr 2016
Application note TI DSP Benchmarking 13 Jan 2016
White paper TI’s processors leading the way in embedded analytics 03 Mar 2015
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 05 Nov 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 05 Nov 2014
Application note OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility (Rev. B) 27 Sep 2013
White paper An architecture for compute-intensive, custom machine vision 14 Mar 2013
Application note Powering the OMAP-L132/OMAP-L137/OMAP-L138 Processor with the TPS650061 13 Apr 2012
White paper MityDSP®-L138F Software Defined Radio Using uPP Data Transfer (Rev. A) 02 Feb 2012
Application note Powering the TMS320C6742, TMS320C6746, and TMS320C6748 With the TPS650061 19 Dec 2011
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F) 14 Sep 2011
Application note High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C) 29 Aug 2011
Application note Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO (Rev. B) 29 Aug 2011
Application note Powering OMAP-L132/L138, C6742/4/6, and AM18x with TPS65070 (Rev. B) 29 Aug 2011
Application note Simple Power Solution Using LDOs (Rev. B) 29 Aug 2011
White paper OpenCV on TI’s DSP+ARM® 27 Jul 2011
Application note TMS320C674x/OMAP-L1x Processor Security 08 Jun 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 19 May 2011
More literature OMAP-L1x C6000 DSP+ARM Processors Product Bulletin (Rev. A) 10 Mar 2011
User guide TMS320C674x DSP Megamodule Reference Guide (Rev. A) 03 Aug 2010
User guide TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) 30 Jul 2010
Application note High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A) 05 May 2010
Application note High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A) 05 May 2010
Application note Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB 25 Nov 2009
Application note TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing 17 Aug 2009
Application note TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing 17 Aug 2009
White paper Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core 24 Jun 2009
Application note TMS320C674x/OMAP-L1x USB Compliance Checklist 12 Mar 2009
User guide TMS320C674x DSP Cache User's Guide (Rev. A) 11 Feb 2009
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 Jul 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CL-3P-L138-SOM — Critical Link system on module based on OMAP-L138 DSP+Arm processor and the Xilinx Spartan 6

The MityDSP-L138F system on module (SOM) includes the OMAP-L138 DSP + Arm® processor and enables users to expand the OMAP-L138 I/O to quickly integrate with an on-board FPGA. It includes industrial embedded instrumentation and is ideal for industrial and real time communications based (...)
From: Critical Link, LLC
Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

In stock
Limit: 3
Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Development kit

TMDSLCDK138 — OMAP-L138 development kit (LCDK)

The OMAP-L138 DSP+Arm9™ development kit will enable fast and easy Linux software and hardware development. This scalable platform will ease and accelerate software and hardware development of everyday applications that require real-time signal processing and control functional, including (...)

In stock
Limit: 5
Development kit

TMDSLCDK6748 — TMS320C6748 DSP development kit (LCDK)

The TMS320C6748 DSP development kit (LCDK) is a scalable platform that breaks down development barriers for applications that require embedded analytics and real-time signal processing, including biometric analytics, communications and audio. The low-cost LCDK will also speed and ease your hardware (...)

In stock
Limit: 16
Software development kit (SDK)

PROCESSOR-SDK-OMAPL138 — Processor SDK for OMAPL138 Processors for Linux and TI-RTOS Support

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
Driver or library

MATHLIB — DSP Math Library for Floating Point Devices

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
Driver or library

SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Driver or library

WIND-3P-VXWORKS-LINUX-OS — Wind River Processors VxWorks and Linux operating systems

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
From: Wind River Systems
IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio؜™ software is an integrated development environment (IDE) that supports TI's microcontroller (MCU) and embedded processor portfolios. Code Composer Studio software comprises a suite of tools used to develop and debug embedded applications. The software includes an (...)
IDE, configuration, compiler or debugger

SECDEVTOOL-OMAPL138C6748 — Basic Secure Boot Development Tools for OMAP-L138 C6000 DSP+ARM Processors & C6748 DSPs

OMAP-L138 C6000 DSP+ARM® processor and TMS320C6748 digital signal processor (DSP) product families offer secure-boot enabled devices which add protection of encrypted application code on the external flash devices and the ability to upgrade boot code and application code remotely while allowing (...)
Operating system (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
From: Mentor Graphics Corporation
Software codec

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VOIP, speech and audio codecs

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
From: Adaptive Digital Technologies, Inc.
Software codec

VOCAL-3P-DSPVOIPCODECS — Vocal technologies DSP VoIP codecs

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)
From: VOCAL Technologies, Ltd.
Simulation model

OMAP-L138 ZWT BSDL Model (Rev. B)

SPRM376B.ZIP (18 KB) - BSDL Model
Simulation model

OMAP-L138 ZCE BSDL Model (Rev. B)

SPRM377B.ZIP (18 KB) - BSDL Model
Simulation model

OMAP-L138 ZWT IBIS Model (Rev. C)

SPRM378C.ZIP (121 KB) - IBIS Model
Simulation model

OMAP-L138 ZCE IBIS Model (Rev. B)

SPRM379B.ZIP (120 KB) - IBIS Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Reference designs

TIDEP0040 — Software Defined Radio (SDR) OMAPL-138-based Hardware/Software Reference Design

Software Defined Radio (SDR) is a popular application within the wireless infrastructure market.  This hardware reference design, leveraging the real time signal processing of the TI DSP and its Universal Parallel Port (uPP), along with TI ADC and DAC, offers SDR algorithm developers a quick (...)
Reference designs

TIDEP0038 — Vision Analytics OMAPL-138-based Hardware/Software Reference Design

Vision analytics is a critical function for many industrial automated applications including machine vision, inspection automation, surveillance and image processing.  This hardware/software design kit is optimized for vision analytic based applications and provides the all of hardware design (...)
Reference designs

PR2084 — Powering the OMAP-L132/OMAP-L137/OMAP-L138 with the TPS650061

This reference design presents a complete power solution and low-cost, discrete sequencing circuit for the OMAP-L132, OMAP-L137, and OMAP-L138 processors.
Package Pins Download
NFBGA (ZCE) 361 View options
NFBGA (ZWT) 361 View options

Ordering & quality

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