SBOS450C July   2009  – August 2014 OPA1611 , OPA1612

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics: VS = ±2.25 V to ±18 V
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Dissipation
      2. 7.3.2 Electrical Overstress
      3. 7.3.3 Operating Voltage
      4. 7.3.4 Input Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Noise Performance
      1. 8.2.1 Detailed Design Procedure
      2. 8.2.2 Application Curve
      3. 8.2.3 Basic Noise Calculations
    3. 8.3 Total Harmonic Distortion Measurements
    4. 8.4 Capacitive Loads
    5. 8.5 Application Circuit
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds while paying attention to the flow of the ground current. For more detailed information, refer to the application report Circuit Board Layout Techniques (SLOA089).
  • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be keep them separate, crossing the sensitive trace perpendicular as opposed to in parallel with the noisy trace is the preferred method.
  • Place the external components as close to the device as possible. As shown in Figure 36, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

10.2 Layout Example

layout_example_bos620.gifFigure 36. Operational Amplifier Board Layout for a Noninverting Configuration