| Offset Voltage Production Distribution | Figure 6-1 to Figure 6-6 |
| Offset Voltage Drift Distribution | Figure 6-7 to Figure 6-8 |
| Offset Voltage vs Temperature | Figure 6-9 |
| Offset Voltage vs Common-Mode Voltage | Figure 6-10 to Figure 6-12 |
| Offset Voltage vs Power Supply | Figure 6-13 |
| Open-Loop Gain and Phase vs Frequency | Figure 6-14 |
| Closed-Loop Gain and Phase vs Frequency | Figure 6-15 |
| Input Bias Current vs Common-Mode Voltage | Figure 6-16 |
| Input Bias Current vs Temperature | Figure 6-17 |
| Output Voltage Swing vs Output Current (maximum supply) | Figure 6-18 |
| CMRR and PSRR vs Frequency | Figure 6-19 |
| CMRR vs Temperature | Figure 6-20 |
| PSRR vs Temperature | Figure 6-21 |
| 0.1-Hz to 10-Hz Noise | Figure 6-22 |
| Input Voltage Noise Spectral Density vs Frequency | Figure 6-23 |
| THD+N Ratio vs Frequency | Figure 6-24 |
| THD+N vs Output Amplitude | Figure 6-25 |
| Quiescent Current vs Supply Voltage | Figure 6-26 |
| Quiescent Current vs Temperature | Figure 6-27 |
| Open Loop Gain vs Temperature | Figure 6-28 |
| Open Loop Output Impedance vs Frequency | Figure 6-29 |
| Small Signal Overshoot vs Capacitive Load (100-mV Output Step) | Figure 6-30, Figure 6-31 |
| No Phase Reversal | Figure 6-32 |
| Positive Overload Recovery | Figure 6-33 |
| Negative Overload Recovery | Figure 6-34 |
| Small-Signal Step Response (100 mV) | Figure 6-35, Figure 6-36 |
| Large-Signal Step Response | Figure 6-37 |
| Settling Time | Figure 6-38 to Figure 6-41 |
| Short-Circuit Current vs Temperature | Figure 6-42 |
| Maximum Output Voltage vs Frequency | Figure 6-43 |
| Propagation Delay Rising Edge | Figure 6-44 |
| Propagation Delay Falling Edge | Figure 6-45 |
| Crosstalk vs Frequency | Figure 6-46 |