SBOS584E November   2011  – June 2018 OPA180 , OPA2180 , OPA4180


  1. Features
  2. Applications
  3. Description
    1.     Low Noise (Peak-to-Peak Noise = 250 nV)
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions: OPA180
    3.     Pin Functions: OPA2180
    4.     Pin Functions: OPA4180
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA180
    5. 7.5 Thermal Information: OPA2180
    6. 7.6 Thermal Information: OPA4180
    7. 7.7 Electrical Characteristics: VS = ±2 V to ±18 V (VS = 4 V to 36 V)
    8. 7.8 Typical Characteristics: Table of Graphs
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Characteristics
      2. 8.3.2 EMI Rejection
      3. 8.3.3 Phase-Reversal Protection
      4. 8.3.4 Capacitive Load and Stability
      5. 8.3.5 Electrical Overstress
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Bipolar ±10-V Analog Output from a Unipolar Voltage Output DAC
        1. Design Requirements
        2. Detailed Design Procedure
          1. Component Selection
        3. Application Curves
      2. 9.2.2 Discrete INA + Attenuation
      3. 9.2.3 RTD Amplifier
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Component Selection

DAC: For convenience, devices with an external reference option or devices with accessible internal references are desirable in this application because the reference creates an offset. The DAC selection in this design must primarily be based on DC error contributions typically described by offset error, gain error, and integral nonlinearity error. Occasionally, additional specifications are provided that summarize end-point errors of the DAC typically called zero-code and full-scale errors. For AC applications, slew rate and settling time may require additional consideration.

Amplifier: Amplifier input offset voltage (VIO) is a key consideration for this design. VIO of an operational amplifier is a typical data sheet specification, but in-circuit performance is also affected by drift over temperature, the common-mode rejection ratio (CMRR), and power-supply rejection ratio (PSRR); thus consideration should be given to these parameters as well. For ac operation, additional considerations should be made concerning slew rate and settling time. Input bias current (IIB) can also be a factor, but typically the resistor network is implemented with sufficiently small resistor values that the effects of input bias current are negligible.

Passive: Resistor matching for the op-amp resistor network is critical for the success of this design; components with tight tolerances must be selected. For this design, 0.1% resistor values are implemented, but this constraint may be adjusted based on application-specific design goals. Resistor matching contributes to offset error and gain error in this design; see Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC for further details. The tolerance of the RISOand CCOMP stability components is not critical, and 1% components are acceptable.