SBOS807E December   2016  – May 2020 OPA187 , OPA2187 , OPA4187

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      OPAx187 Offers Precision Low-Side Current Measurement Capability
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: OPA187
    2.     Pin Functions: OPA2187
    3.     Pin Functions: OPA4187
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA187
    5. 6.5 Thermal Information: OPA2187
    6. 6.6 Thermal Information: OPA4187
    7. 6.7 Electrical Characteristics: High-Voltage Operation
    8. 6.8 Electrical Characteristics: Low-Voltage Operation
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Input Bias Current Clock Feedthrough
      4. 7.3.4 Internal Offset Correction
      5. 7.3.5 EMI Rejection
      6. 7.3.6 Capacitive Load and Stability
      7. 7.3.7 Electrical Overstress
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Voltage-to-Current (V-I) Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
      3. 8.2.3 Bridge Amplifier
      4. 8.2.4 Low-Side Current Monitor
      5. 8.2.5 Programmable Power Supply
      6. 8.2.6 RTD Amplifier With Linearization
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Low-ESR, 0.1-µF ceramic bypass capacitors must be connected between each supply pin and ground; place the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply applications.
  • To reduce parasitic coupling, run the input traces as far away from the supply lines as possible.
  • A ground plane helps distribute heat and reduces EMI noise pickup.
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.