SBOS957D February   2022  – December 2023 OPA2328 , OPA328

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - OPA328
    5. 5.5 Thermal Information - OPA2328
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input and ESD Protection
      2. 6.3.2 Rail-to-Rail Input
      3. 6.3.3 Phase Reversal
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Capacitive Load and Stability
    2. 7.2 Typical Applications
      1. 7.2.1 Bidirectional Current-Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Transimpedance Amplifier
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 DIP-Adapter-EVM
        4. 8.1.1.4 DIYAMP-EVM
        5. 8.1.1.5 Filter Design Tool
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

at TA = 25°C, VS = ±1.1 V to ±2.75 V (VS = 2.2 V to 5.5 V), RL = 10 kΩ connected to VS / 2, VCM = VOUT = VS / 2, and min and max specification established from manufacturing final test (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage OPA2328D, DGK, and DRG ±3 ±50 μV
OPA328DBV ±3 ±75
dVOS/dT Input offset voltage drift TA = –40°C to +125°C OPA328DBV, OPA2328D, DGK ±0.15 ±1 μV/°C
OPA2328DRG ±0.15 ±1.5
PSRR Power-supply rejection ratio VS = ±1.1 V to ±2.75 V ±1 ±10 μV/V
VS = ±1.1 V to ±2.75 V, TA = –40°C to +125°C ±15 ±40
Channel separation (dual, quad) f = dc 140 dB
f = 100 kHz 75
INPUT BIAS CURRENT
IB Input bias current ±0.2 ±1 pA
TA = 0°C to 85°C 10
TA = –40°C to +125°C 100
IOS Input offset current ±0.2 ±1 pA
TA = 0°C to 85°C 10
TA = –40°C to +125°C 100
NOISE
  Input voltage noise f = 0.1 Hz to 10 Hz   3   μVPP
eN Input voltage noise density f = 100 Hz   25   nV/√Hz
f = 1 kHz   9.8  
f = 10 kHz   6.1  
iN Input current noise f = 10 kHz   0.125   pA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio (V–) – 0.1 V < VCM < (V+) + 0.1 V 106 120 dB
TA = –40°C to +125°C 96 110
INPUT CAPACITANCE
ZID Differential 1 || 4 TΩ || pF
ZICM Common-mode 1 || 2 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 100 mV < VO < (V+) – 100 mV 108 132 dB
TA = –40°C to +125°C 96 130
(V–) + 200 mV < VO < (V+) – 200 mV,
RL = 2 kΩ		 106 123
TA = –40°C to +125°C 90
FREQUENCY RESPONSE
GBW Gain-bandwidth product Gain = 100 40 MHz
SR Slew rate 4-V step, gain = +1 30 V/μs
tS Settling time To 0.1%, 1-V step, gain = +1 0.1 μs
To 0.01%, 1-V step, gain = +1 0.18
Overload recovery time VIN × gain > VS 0.5 μs
THD+N Total harmonic distortion + noise VO = 1 VRMS, gain = +1, f = 1 kHz 0.0001 %
OUTPUT
Voltage output swing from both rails VS = 2.2 V 5 mV
RL = 2 kΩ 15
VS = 5.5 V OPA328DBV, OPA2328D, DGK 5
OPA2328DRG 10
RL = 2 kΩ, 
OPA328DBV, OPA2328D, DGK		 15
RL = 2 kΩ, 
OPA2328DRG		 20
ISC Short-circuit current Sinking, VS = 5.5 V –65 mA
Sourcing, VS = 5.5 V 55
CLOAD Capacitive load drive Gain = +1 28 pF
RO Open-loop output impedance f = 10 kHz 55 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 3.8 4.5 mA
IO = 0 A, TA = –40°C to +125°C 5.0
SHUTDOWN (OPA328SDBV and OPA4328RUM)
IQSD Quiescent current in shutdown All amplifiers disabled 30 50 µA
ZOFF Output impedance in shutdown All amplifiers disabled 100 || 16 GΩ || pF
VIH High-level input voltage Amplifier enabled (V+) – 0.5 V
VIL Low-level input voltage Amplifier disabled (V–) + 0.5 V
tON Output enable time G = 1, VOUT = 0.9 × VS/2, all amplifiers enabled 10 µs
tOFF Output disable time G = 1, VOUT = 0.1 × VS/2, all amplifiers disabled 3 µs
EN pin input leakage
current		 VIH = V+ 0.02 µA
VIL = V– 1