SBOSAA1G April   2022  – January 2024 OPA2310 , OPA310 , OPA4310

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Rail-to-Rail Input
      3. 7.3.3  Rail-to-Rail Output
      4. 7.3.4  Capacitive Load and Stability
      5. 7.3.5  Overload Recovery
      6. 7.3.6  EMI Rejection
      7. 7.3.7  ESD and Electrical Overstress
      8. 7.3.8  Input ESD Protection
      9. 7.3.9  Shutdown Function
      10. 7.3.10 Packages with an Exposed Thermal Pad
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 OPAx310 Low-Side, Current Sensing Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4.     Trademarks
    5. 9.4 Electrostatic Discharge Caution
    6. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-317CAF4D-8D89-4FF7-B31E-848C54BC3F00-low.svgFigure 5-1 OPA310 DBV Package,
5-Pin SOT-23
(Top View)
GUID-A8411408-22C0-4DC6-BC3E-B1C594974B26-low.svgFigure 5-3 OPA310 DPW Package,
5-Pin X2SON
(Top View)
GUID-2CDE5739-0734-4A9E-AA87-D929675E685E-low.svgFigure 5-2 OPA310 DCK and DRL Package,
5-Pin SC70 and 5-Pin SOT-5X3
(Top View)
Table 5-1 Pin Functions: OPA310
PIN (1)TYPE DESCRIPTION
NAME SOT-23 SC70, SOT-5X3 X2SON
IN– 4 3 2 I Inverting input
IN+ 3 1 4 I Noninverting input
OUT 1 4 1 O Output
V– 2 2 3 I Negative (low) supply or ground (for single-supply operation)
V+ 5 5 5 I Positive (high) supply
(1) I = input, O = output
GUID-1E0BE458-E250-4476-AE27-B276A7D9D51A-low.svgFigure 5-4 OPA310S DBV Package,
6-Pin SOT-23
(Top View)
GUID-DAA8F089-7E03-491A-8007-E7FF54A00F31-low.gifFigure 5-5 OPA310S DCK Package,
6-Pin SC70
(Top View)
Table 5-2 Pin Functions: OPA310S
PIN (1)TYPE DESCRIPTION
NAME SOT-23 SC70
IN– 4 3 I Inverting input
IN+ 3 1 I Noninverting input
OUT 1 4 O Output
SHDN 5 5 I Shutdown: low = amp disabled, high = amp enabled
See Shutdown Function for more information
V– 2 2 I Negative (low) supply or ground (for single-supply operation)
V+ 6 6 I Positive (high) supply
(1) I = input, O = output
GUID-4A206688-C483-4CE5-BEAD-9DBFEEC0C60F-low.svgFigure 5-6 OPA2310 D, DDF, DGK, and PW Package,
8-Pin SOIC, SOT-23-THIN, VSSOP, and TSSOP
(Top View)
GUID-54D7EC22-ED76-4714-9691-861026A474D6-low.svg
Connect exposed thermal pad to V–. See Section 7.3.10 for more information.
Figure 5-7 OPA2310 DSG Package,
8-Pin WSON with Exposed Thermal Pad
(Top View)
Table 5-3 Pin Functions: OPA2310
PIN (1)TYPE DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V– 4 I Negative (low) supply or ground (for single-supply operation)
V+ 8 I Positive (high) supply
(1) I = input, O = output
GUID-7CB88CA5-6553-4A4F-A912-312C0D3C2C3B-low.svgFigure 5-8 OPA2310S RUG Package,
10-Pin X2QFN
(Top View)
GUID-20220425-CA0I-Z5H5-ZN9K-QSHVW00LCJX6-low.svgFigure 5-9 OPA2310S DGQ Package,
10-Pin HVSSOP
(Top View)
Table 5-4 Pin Functions: OPA2310S
PIN (1)TYPE DESCRIPTION
NAME X2QFN HVSSOP
IN1– 9 2 I Inverting input, channel 1
IN1+ 10 3 I Noninverting input, channel 1
IN2– 5 7 I Inverting input, channel 2
IN2+ 4 8 I Noninverting input, channel 2
OUT1 8 1 O Output, channel 1
OUT2 6 9 O Output, channel 2
SHDN1 2 5 I Shutdown: low = amp disabled, high = amp enabled, channel 1
See Shutdown Function for more information
SHDN2 3 6 I Shutdown: low = amp disabled, high = amp enabled, channel 2
See Shutdown Function for more information
V– 1 4 I Negative (low) supply or ground (for single-supply operation)
V+ 7 10 I Positive (high) supply
(1) I = input, O = output
GUID-656BD182-AA6E-4857-8072-F35688ECA4BF-low.svgFigure 5-10 OPA4310 D and PW Package,
14-Pin SOIC and TSSOP
(Top View)
GUID-796E40CC-EF3E-4F3E-BC77-B8470261F387-low.svgFigure 5-11 OPA4310 RUC Package,
14-Pin X2QFN
(Top View)
Table 5-5 Pin Functions: OPA4310
PIN (1)TYPE DESCRIPTION
NAME SOIC, TSSOP X2QFN
IN1– 2 1 I Inverting input, channel 1
IN1+ 3 2 I Noninverting input, channel 1
IN2– 6 5 I Inverting input, channel 2
IN2+ 5 4 I Noninverting input, channel 2
IN3– 9 8 I Inverting input, channel 3
IN3+ 10 9 I Noninverting input, channel 3
IN4– 13 12 I Inverting input, channel 4
IN4+ 12 11 I Noninverting input, channel 4
OUT1 1 14 O Output, channel 1
OUT2 7 6 O Output, channel 2
OUT3 8 7 O Output, channel 3
OUT4 14 13 O Output, channel 4
V– 11 10 I Negative (low) supply or ground (for single-supply operation)
V+ 4 3 I Positive (high) supply
(1) I = input, O = output
GUID-F4917F55-7797-4253-8696-2326F614AB1C-low.svg
A. Connect thermal pad to V–.
Figure 5-12 OPA4310S RTE Package,
16-Pin WQFN With Exposed Thermal Pad
(Top View)
GUID-20220425-CA0I-LL23-4RXS-PZLLWNS5564H-low.svg
A. Connect thermal pad to V–.
Figure 5-13 OPA4310S DYY Package,
16-Pin SOT-23-THIN
(Top View)
Table 5-6 Pin Functions: OPA4310S
PIN (1)TYPE DESCRIPTION
NAME WQFN SOT-23-THIN
IN1+ 1 3 I Noninverting input, channel 1
IN1– 16 2 I Inverting input, channel 1
IN2+ 3 5 I Noninverting input, channel 2
IN2– 4 6 I Inverting input, channel 2
IN3+ 10 12 I Noninverting input, channel 3
IN3– 9 11 I Inverting input, channel 3
IN4+ 12 14 I Noninverting input, channel 4
IN4– 13 15 I Inverting input, channel 4
SHDN12 6 8 I Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2.
See Shutdown Function for more information
SHDN34 7 9 I Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4.
See Shutdown Function for more information
OUT1 15 1 O Output, channel 1
OUT2 5 7 O Output, channel 2
OUT3 8 10 O Output, channel 3
OUT4 14 16 O Output, channel 4
V– 11 13 I Negative (low) supply or ground (for single-supply operation)
V+ 2 4 I Positive (high) supply