SBOSAC9E August   2022  – July 2024 OPA2992-Q1 , OPA4992-Q1 , OPA992-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 Common-Mode Voltage Range
      6. 6.3.6 Phase Reversal Protection
      7. 6.3.7 Electrical Overstress
      8. 6.3.8 Overload Recovery
      9. 6.3.9 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7V to 40V (±1.35V to ±20V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.21 ±1.03 mV
TA = –40°C to 125°C ±1.2
dVOS/dT Input offset voltage drift VCM = V– TA = –40°C to 125°C ±0.25 µV/℃
PSRR Input offset voltage versus power supply OPA992-Q1, OPA2992-Q1, VCM = V–, VS = 5V to 40V TA = –40°C to 125°C ±0.2 ±1.3 μV/V
OPA4992-Q1, VCM = V–, VS = 5V to 40V ±0.4 ±1.8
OPA992-Q1, OPA2992-Q1, OPA4992-Q1, VCM = V–, VS = 2.7V to 40V(1) ±0.8 ±7
DC channel separation 0.4 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±10 pA
NOISE
EN Input voltage noise f = 0.1Hz to 10Hz   2.77 μVPP
  0.49   µVRMS
eN Input voltage noise density f = 1kHz 7   nV/√Hz
f = 10kHz   4.4  
iN Input current noise density f = 1kHz   60   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) (V+) V
CMRR Common-mode rejection ratio VS = 40V, V– < VCM < (V+) – 2V (PMOS pair) TA = –40°C to 125°C 100 115 dB
VS = 5V, V– < VCM < (V+) – 2V (PMOS pair)(1) 75 98
VS = 2.7V, V– < VCM < (V+) – 2V (PMOS pair) 90
VS = 2.7 – 40V, (V+) – 1V < VCM < V+ (NMOS pair) 79
(V+) – 2V < VCM < (V+) – 1V See Offset Voltage vs CommonMode Voltage (Transition Region)
INPUT IMPEDANCE
ZID Differential 100 || 9 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V		 120 142 dB
VS = 40V, VCM = VS / 2,
(V–) + 0.12V < VO < (V+) –  0.12V		 TA = –40°C to 125°C 142
VS = 5V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V(1)		 104 125
TA = –40°C to 125°C 125
VS = 2.7V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V(1)		 90 105
TA = –40°C to 125°C 105
FREQUENCY RESPONSE
GBW Gain-bandwidth product 10.6 MHz
SR Slew rate VS = 40V, G = +1, VSTEP = 10V, CL = 20pF(3) 32 V/μs
tS Settling time To 0.1%, VS = 40V, VSTEP = 10V, G = +1, CL = 20pF 0.65 μs
To 0.1%, VS = 40V, VSTEP = 2V, G = +1, CL = 20pF 0.3
To 0.01%, VS = 40V, VSTEP = 10V, G = +1, CL = 20pF 0.86
To 0.01%, VS = 40V, VSTEP = 2V, G = +1, CL = 20pF 0.44
Phase margin G = +1, RL = 10kΩ, CL = 20pF 64 °
Overload recovery time VIN  × gain > VS 170 ns
THD+N Total harmonic distortion + noise VS = 40V, VO = 3VRMS, G = 1, f = 1kHz, RL = 10kΩ 0.00005%
126 dB
VS = 10V, VO = 3VRMS, G = 1, f = 1kHz, RL = 128Ω 0.0032%
90 dB
VS = 10V, VO = 0.4VRMS, G = 1, f = 1kHz, RL = 32Ω 0.00032%
110 dB
OUTPUT
  Voltage output swing from rail Positive and negative
rail headroom		 VS = 40V, RL = no load   7 mV
VS = 40V, RL = 10kΩ   48 60
VS = 40V, RL = 2kΩ   220 300
VS = 2.7V, RL = no load   0.5
VS = 2.7V, RL = 10kΩ   5 20
VS = 2.7V, RL = 2kΩ   20 50
ISC Short-circuit current ±65(2) mA
CLOAD Capacitive load drive See Phase Margin vs Capacitive Load pF
ZO Open-loop output impedance IO = 0A See Open-Loop Output Impedance vs Frequency Ω
POWER SUPPLY
IQ Quiescent current per amplifier OPA2992-Q1, OPA4992-Q1, IO = 0A 2.4 2.8 mA
TA = –40°C to 125°C 2.84
OPA992, IO = 0A 2.48 2.92
TA = –40°C to 125°C 2.98
(1) Specified by characterization only.
(2) At high supply voltage, placing the OPAx992 in a sudden short to mid-supply or ground will lead to rapid thermal shutdown.  Output current greater than ISC can be achieved if rapid thermal shutdown is avoided as per Output Voltage Swing vs Output Current.
(3) See Slew Rate vs Input Step Voltage for more information.