SBOSA94 November   2021 OPA4H014-SEP

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Capacitive Load and Stability
      2. 7.3.2 Output Current Limit
      3. 7.3.3 Phase-Reversal Protection
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Performance
        1. 8.1.1.1 Basic Noise Calculations
      2. 8.1.2 Electrical Overstress
      3. 8.1.3 EMI Rejection
      4. 8.1.4 EMIRR +IN Test Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 PSpice® for TI
        2. 11.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 11.1.1.3 WEBENCH® Filter Designer Tool
        4. 11.1.1.4 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1.    

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Radiation hardened
    • Single even latch-up (SEL) immune to 43 MeV•cm2/mg
    • ELDRS free to 30 krad(Si)
    • Total ionizing dose (TID) RLAT for every wafer lot up to 30 krad(Si)
  • Space enhanced plastic
    • Au bondwire and NiPdAu lead finish
    • Enhanced mold compound for low outgassing
    • One fabrication, assembly, and test site
    • Extended product life cycle
    • Extended product change notification
    • Product traceability
  • Very-low offset drift: 1 μV/°C maximum
  • Very-low offset: 120 μV
  • Low input bias current: 10 pA maximum
  • Low noise: 5.1 nV/√Hz
  • Slew rate: 20 V/μs
  • Low supply current: 2 mA maximum
  • Input voltage range includes V– supply
  • Wide supply range: 4.5 V to 18 V