SBOS673D September   2017  – December 2018

PRODUCTION DATA.

1. Features
2. Applications
3. Description
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Detailed Description
1. 7.1 Overview
2. 7.2 Functional Block Diagrams
3. 7.3 Feature Description
4. 7.4 Device Functional Modes
8. Application and Implementation
1. 8.1 Application Information
2. 8.2 Typical Applications
1. 8.2.1 Active Filters
2. 8.2.2 Implementing a 2:1 Active Multiplexer
3. 8.2.3 1-Bit PGA Operation
9. Power Supply Recommendations
10. 10Layout
11. 11Device and Documentation Support
12. 12Mechanical, Packaging, and Orderable Information

• DCK|5
• DBV|6
• DCK|5

#### 8.1.3 Output DC Error Calculations

The OPAx837 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise input stage for the OPAx837 has a relatively high input bias current (0.34 µA typical out the pins) but with a close match between the two input currents. The OPAx837 is a negative rail input device using PNP input devices where the base current flows out of the device pins. A large resistor to ground on the V+ input shifts the pin voltage positively because of the input bias current. The mismatch between the two input bias currents is very low, typically only ±10 nA of input offset current. Match the DC source impedances out of the two inputs to reduce the total output offset voltage. Figure 67 illustrates an example of resistor matching for bias current cancellation. Analyzing the simple circuit of Figure 67 (using a gain of 2-V/V target with RF = RG = 2 kΩ) illustrates that the noise gain for the input offset voltage drift is 1 + 2 kΩ / 2 kΩ = 2 V/V. This value results in an output drift term of ±1.6 µV/°C × 2 = ±3.2 µV/°C (DCK package). Because the two impedances out of the inputs are matched, the residual error from the maximum ±250 pA/°C offset current drift is this maximum IOS drift times the 2-kΩ feedback resistor value, or ±50 µV/°C. The total output DC error drift band is ±53.2 µV/°C. If the output DC drift is more important than reduced feedback currents, lower the resistor values to reduce the dominant drift term resulting from the IOS term.