SBOS867C August 2017 – October 2023 OPA838
PRODUCTION DATA
The OPA838 can provide excellent DC signal accuracy due to high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise input stage for the OPA838 has a relatively high input bias current (1.6 µA typical out the pins) but with a close match between the two input currents. This is a negative rail input device using PNP input devices where the base current flows out of the device pins. A large resistor to ground on the V+ input shifts positively because of the input bias current. The mismatch between the two input bias currents is very low, typically only ±20 nA of input offset current. Match the DC source impedances out of the two inputs to reduce the total output offset voltage. For example, one way to add bias current cancellation to the circuit in Figure 8-8 is to insert a 165-Ω series resistor into the noninverting input to match the parallel combination of RF and RG for this basic gain of 6 V/V noninverting gain circuit. These same calculations apply to the output offset drift. Analyzing the simple circuit of Figure 8-8, the noise gain for the input offset voltage drift is 1 + 1k / 200 = 6 V/V. This results in an output drift term of ±1.6 µV/°C × 6 = ±9.6 µV/°C. Because the two impedances out of the inputs are matched, the residual error due to the maximum ±500 pA/°C offset current drift is exactly that number times the 1-kΩ feedback resistor value, or ±50 µV/°C. The total output DC error drift band is ±59 µV/°C.