SBOS681C July   2014  – November 2017 OPT3001


  1. Features
  2. Applications
    1.     Spectral Response: The OPT3001 and Human Eye
  3. Description
    1.     Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Human Eye Matching
      2. 7.3.2 Automatic Full-Scale Range Setting
      3. 7.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 7.3.4 I2C Bus Overview
        1. Serial Bus Address
        2. Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Automatic Full-Scale Setting Mode
      2. 7.4.2 Interrupt Reporting Mechanism Modes
        1. Latched Window-Style Comparison Mode
        2. Transparent Hysteresis-Style Comparison Mode
        3. End-of-Conversion Mode
        4. End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 7.5 Programming
      1. 7.5.1 Writing and Reading
        1. High-Speed I2C Mode
        2. General-Call Reset Command
        3. SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 Internal Registers
        1. Register Descriptions
          1. Result Register (offset = 00h)
            1. Table 7. Result Register Field Descriptions
          2. Configuration Register (offset = 01h) [reset = C810h]
            1. Table 10. Configuration Register Field Descriptions
          3. Low-Limit Register (offset = 02h) [reset = C0000h]
            1. Table 11. Low-Limit Register Field Descriptions
          4. High-Limit Register (offset = 03h) [reset = BFFFh]
            1. Table 13. High-Limit Register Field Descriptions
          5. Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
            1. Table 14. Manufacturer ID Register Field Descriptions
          6. Device ID Register (offset = 7Fh) [reset = 3001h]
            1. Table 15. Device ID Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Optomechanical Design
        2. Dark Window Selection and Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Soldering and Handling Recommendations
    2. 12.2 DNP (S-PDSO-N6) Mechanical Drawings

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Latched Window-Style Comparison Mode

The latched window-style comparison mode is typically selected when using the OPT3001 to interrupt an external processor. In this mode, a fault is recognized when the input signal is above the high-limit register or below the low-limit register. When the consecutive fault events trigger the interrupt reporting mechanisms, these mechanisms are latched, thus reporting whether the fault is the result of a high or low comparison. These mechanisms remain latched until the configuration register is read, which clears the INT pin and flag high and flag low fields. The SMBus alert response protocol, described in detail in the SMBus Alert Response section, clears the pin but does not clear the flag high and flag low fields. The behavior of this mode, along with the conversion ready flag, is summarized in Table 2. Note that Table 2 does not apply when the two threshold low register MSBs (see the Transparent Hysteresis-Style Comparison Mode section for clarification on the MSBs) are set to 11b.

Table 2. Latched Window-Style Comparison Mode: Flag Setting and Clearing Summary(2)(4)

The result register is above the high-limit register for fault count times. See the Result Register and the High-Limit Register for further details. 1 X Active 1
The result register is below the low-limit register for fault count times. See the Result Register and the Low-Limit Register for further details. X 1 Active 1
The conversion is complete with fault count criterion not met X X X 1
Configuration register read(3) 0 0 Inactive 0
Configuration register write, M[1:0] = 00b (shutdown) X X X X
Configuration register write, M[1:0] > 00b (not shutdown) X X X 0
SMBus alert response protocol X X Inactive X
The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low) or when the pin state is inactive and POL = 1 (active high).
X = no change from the previous state.
Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low field can take on different behaviors.