SCPS128D July   2006  – March 2021 PCA9554


  1. Features
  2. Description
  3. Revision History
  4. Description (Continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
      1. 8.2.1 Power-On Reset
      2. 8.2.2 I/O Port
      3. 8.2.3 Interrupt Output ( INT)
        1. Interrupt Errata
          1.        23
          2. 24
          3. 25
    3. 8.3 Programming
      1. 8.3.1 I2C Interface
      2. 8.3.2 Register Map
        1. Device Address
        2. Control Register And Command Byte
        3. Register Descriptions
        4. Bus Transactions
          1. Writes
          2. Reads
  9. Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. Design Requirements
          1. Minimizing ICC When I/Os Control Leds
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Interrupt Output ( INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.

Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.

The INT output has an open-drain structure and requires pullup resistor to VCC.