SBAS448B October   2008  – August 2015 PCM1690

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Digital Input/Output
    6. 6.6  Electrical Characteristics: DAC
    7. 6.7  Electrical Characteristics: Power-Supply Requirements
    8. 6.8  System Clock Timing Requirements
    9. 6.9  Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I2S Data Formats
    10. 6.10 Audio Interface Timing Requirements for DSP and TDM Data Formats
    11. 6.11 Three-Wire Serial Control Interface Timing Requirements
    12. 6.12 SCL and SDA Control Interface Timing Requirements
    13. 6.13 Typical Characteristics
      1. 6.13.1 Digital Filter
      2. 6.13.2 Digital De-Emphasis Filter
      3. 6.13.3 Dynamic Performance
      4. 6.13.4 Output Spectrum
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Outputs
      2. 7.3.2  Voltage Reference VCOM
      3. 7.3.3  System Clock Input
      4. 7.3.4  Sampling Mode
      5. 7.3.5  Reset Operation
      6. 7.3.6  Zero Flag
      7. 7.3.7  AMUTE Control
      8. 7.3.8  Three-Wire (SPI) Serial Control
      9. 7.3.9  Control Data Word Format
      10. 7.3.10 Register Write Operation
      11. 7.3.11 Two-Wire (I2C) Serial Control
      12. 7.3.12 Packet Protocol
      13. 7.3.13 Write Operation
      14. 7.3.14 Read Operation
      15. 7.3.15 Timing Requirements: SCL and SDA
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Serial Port Operation
      2. 7.4.2 Audio Data Interface Formats and Timing
      3. 7.4.3 Synchronization With the Digital Audio System
      4. 7.4.4 Mode Control
      5. 7.4.5 Parallel Hardware Control
    5. 7.5 Register Maps
      1. 7.5.1 Control Register Definitions (Software Mode Only)
      2. 7.5.2 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Lowpass Filter and Differential-to-Single-Ended Converter for DAC Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware Control Method
        2. 8.2.2.2 Audio Input
        3. 8.2.2.3 Audio Output
        4. 8.2.2.4 Master Clock
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCA|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DCA Package
48-Pin HTSSOP With PowerPAD
Top View
PCM1690 po_bas448.gif

Pin Functions

PIN I/O PULLDOWN 5-V TOLERANT DESCRIPTION
NAME PIN
RSV2 1 — — — Reserved, tied to analog ground
RSV1 2 — — — Reserved, left open
RSV2 3 — — — Reserved, tied to analog ground
RSV1 4 — — — Reserved, left open
RSV2 5 — — — Reserved, tied to analog ground
LRCK 6 I Yes No Audio data word clock input
BCK 7 I Yes No Audio data bit clock input
DIN1 8 I No No Audio data input for DAC1 and DAC2
DIN2 9 I No No Audio data input for DAC3 and DAC4
DIN3 10 I No No Audio data input for DAC5 and DAC6
DIN4 11 I No No Audio data input for DAC7 and DAC8
VDD 12 — — — Digital power supply, +3.3 V
DGND 13 — — — Digital ground
SCKI 14 I No Yes System clock input
RST 15 I Yes Yes Reset and power-down control input with active low
ZERO1 16 O No No Zero detect flag output 1
ZERO2 17 O No No Zero detect flag output 2
AMUTEI 18 I No Yes Analog mute control input with active low
AMUTEO 19 O No Yes Analog mute status output(1) with active low
MD/SDA/DEMP 20 I/O No Yes Input data for SPI, data for I2C(1), de-emphasis control for hardware control mode
MC/SCL/FMT 21 I No Yes Clock for SPI, clock for I2C, format select for hardware control mode
MS/ADR0/RSV 22 I Yes Yes Chip Select for SPI, address select 0 for I2C, reserve (set low) for hardware control mode
TEST/ADR1/RSV 23 I/O No Yes Test (factory use, left open) for SPI, address select 1 for I2C, reserve (set low) for hardware control mode
MODE 24 I No No Control port mode selection. Tied to VDD: SPI, left open: H/W mode, tied to DGND: I2C
VCC1 25 — — — Analog power supply 1, +5 V
VCOM 26 — — — Voltage common decoupling
AGND1 27 — — — Analog ground 1
RSV2 28 — — — Reserved, tied to analog ground
VOUT8+ 29 O No No Positive analog output from DAC8
VOUT8- 30 O No No Negative analog output from DAC8
VOUT7+ 31 O No No Positive analog output from DAC7
VOUT7- 32 O No No Negative analog output from DAC7
VOUT6+ 33 O No No Positive analog output from DAC6
VOUT6- 34 O No No Negative analog output from DAC6
VOUT5+ 35 O No No Positive analog output from DAC5
VOUT5- 36 O No No Negative analog output from DAC5
VOUT4+ 37 O No No Positive analog output from DAC4
VOUT4- 38 O No No Negative analog output from DAC4
VOUT3+ 39 O No No Positive analog output from DAC3
VOUT3- 40 O No No Negative analog output from DAC3
VOUT2+ 41 O No No Positive analog output from DAC2
VOUT2- 42 O No No Negative analog output from DAC2
VOUT1+ 43 O No No Positive analog output from DAC1
VOUT1- 44 O No No Negative analog output from DAC1
RSV2 45 — — — Reserved, tied to analog ground
AGND2 46 — — — Analog ground 2
VCC2 47 — — — Analog power supply 2, +5 V
RSV2 48 — — — Reserved, tied to analog ground
(1) Open-drain configuration in out mode.